mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 102

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
Data Sheet
102
Addr.
HVOCR[1:0]
$003A
$003F
$0038
$0039
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
00
01
10
11
H&V Sync Output Control
PLL Bandwidth Control
Register Name
PLL Control Register
Register Settings
PLL Programming
Table 8-1. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
MUL[7:4]
(HVOCR)
3
5
8
9
Register
(PBWC)
Register
Register
(PCTL)
(PPG)
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
VRS[7:4]
Figure 8-2. CGM I/O Register Summary
3
3
6
9
PLLIE
AUTO
MUL7
Bit 7
0
0
0
Clock Generator Module (CGM)
Frequency
= Unimplemented
31.45kHz
37.87kHz
48.37kHz
64.32kHz
LOCK
MUL6
HOUT
PLLF
6
0
0
1
PLLON
MUL5
ACQ
5
1
0
1
Output Pin
Frequency
59.91Hz
60.31Hz
60.31Hz
60.00Hz
VOUT
DCLKPH1 DCLKPH0
MUL4
BCS
XLD
4
0
0
0
0
Frequency
108MHz
24MHz
40MHz
64MHz
VRS7
DCLK
R
3
1
1
0
0
0
0
MC68HC908LD64
= Reserved
VRS6
Freescale Semiconductor
2
1
1
0
0
1
R
SXGA 1280 × 1024
SVGA 800 × 600
XGA 1024 × 768
DE Video Mode
VGA 640 × 480
Video Modes
HVOCR1 HVOCR0
VRS5
1
1
1
0
0
1
0
—
Rev. 3.0
VRS4
Bit 0
1
1
0
0
0
0