mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 243

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC908LD64
Freescale Semiconductor
Rev. 3.0
BR2–BR0 — Baud Rate Select
These three bits select one of eight clock rates as the master clock
when the module is in master mode.
Since this master clock is derived the CPU bus clock, the user
program should not execute the WAIT instruction when the DDC
module in master mode. This will cause the SDA and SCL lines to
hang, as the WAIT instruction places the MCU in wait mode, with CPU
clock is halted. These bits are cleared upon reset. (See
Baud Rate
NOTE:
CPU bus clock is external clock ÷ 4 = 6MHz
BR2
Select.)
0
0
0
0
1
1
1
1
DDC12AB Interface
Table 16-2. Baud Rate Select
BR1
0
0
1
1
0
0
1
1
BR0
0
1
0
1
0
1
0
1
Baud Rate
3.125k
12.5k
6.25k
1.56k
0.78k
100k
50k
25k
DDC12AB Interface
Table 16-2 .
DDC Registers
Data Sheet
243

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