mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 177

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

RPF —Reception-in-Progress Flag
13.7.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
13.7.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
Freescale Semiconductor
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
Reading address $003D accesses the read-only received data bits, R7:R0. Writing to address $003D
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
These read/write bits select the baud rate prescaler divisor as shown in
and SCP0.
1 = Reception in progress
0 = No reception in progress
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
$003D
$003E
Bit 7
Bit 7
R7
T7
R
R
0
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 13-15. SCI Baud Rate Register (SCBR)
= Reserved
Figure 13-14. SCI Data Register (SCDR)
SCP1:SCP0
R6
Table 13-5. SCI Baud Rate Prescaling
T6
6
6
0
R
0
00
01
10
11
SCP1
R5
T5
5
5
0
Unaffected by reset
SCP0
R4
T4
4
4
0
Prescaler Divisor (PD)
R3
T3
R
3
3
0
0
13
1
3
4
SCR2
R2
T2
2
2
0
Table
SCR1
R1
T1
1
1
0
13-5. Reset clears SCP1
SCR0
Bit 0
Bit 0
R0
T0
0
I/O Registers
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