mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 267

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

19.5 DC Electrical Characteristics
Freescale Semiconductor
Output high voltage
Output low voltage
PWM pin output source current
PWM pin output sink current (V
Input high voltage, all ports, IRQs, RESET, OSC1
Input low voltage, all ports, IRQs, RESET, OSC1
V
I/O ports high-impedance leakage current
Input current (input only pins)
Capacitance
Low-voltage inhibit reset
Low-voltage reset/recover hysteresis
Low-voltage inhibit reset recovery
Low-voltage inhibit reset
Low-voltage reset/recover hysteresis
Low-voltage inhibit reset recovery
POR re-arm voltage
POR rise time ramp rate
POR reset voltage
Monitor mode entry voltage (on IRQ)
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I
4. Wait I
5. Stop I
6. The low-voltage inhibit reset is software selectable. Refer to
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
9. Maximum is highest voltage that POR is possible.
DD
(I
(I
(V
Run
Wait
Stop
Ports (as input or output)
(V
(V
loads; less than 100 pF on all outputs. C
affects run I
than 100 pF on all outputs. C
measured with PLL and LVI enabled.
combination of V
is reached.
Load
Load
OH
REC1
REC2
DD
supply current
(3)
(4)
(5)
= V
= 5.0 Vdc ± 10%, V
= –2.0 mA) all I/O pins
= 1.6 mA) all I/O pins
DD
DD
= V
= V
DD
measured using external square wave clock source (f
measured with PLL and LVI disengaged, OCS1 grounded, no port pins sourcing current. It is measured through
LVR1
LVR2
–0.8 V)
DD
DD
; measured with all modules enabled
+ V
+ V
(9)
is not reached before the internal POR is released, RST must be driven low externally until minimum V
DD
DD
(7)
Characteristic
LVH1
LVH2
, V
measured using external square wave clock source (f
(6)
(8)
DDAD
)
)
SS
= 0 Vdc, T
, and V
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
OL
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I
= 0.8 V)
(1)
DDA
A
.
= T
L
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly
to T
H
, unless otherwise noted.
V
Symbol
V
V
Chapter 9 Low-Voltage Inhibit
V
V
V
V
PORRST
R
V
C
V
V
I
V
I
C
REC1
REC2
V
I
V
LVR1
LVH1
LVR2
LVH2
I
I
POR
POR
OSC
OH
DD
OL
OH
Out
OL
IL
In
IH
Hi
IL
In
= 8.2 MHz); all inputs 0.2 V from rail; no dc loads; less
OSC
0.7 x V
V
V
DD
DD
0.035
4.04
3.85
Min
V
150
4.0
4.0
–7
20
40
—
—
—
—
—
—
—
—
= 8.2 MHz). All inputs 0.2 V from rail; no dc
0
0
SS
+ 2.5
–0.8
DD
Typ
4.35
4.15
210
700
(LVI).
4.5
4.4
DC Electrical Characteristics
90
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
0.3 x V
Max
4.65
4.75
4.45
V
700
±10
150
250
100
800
0.4
4.6
8.0
30
12
±1
12
—
—
—
—
8
DD
DD
V/ms
Unit
mA
mA
mV
mV
mV
mA
mA
µA
µA
µA
pF
V
V
V
V
V
V
V
V
V
V
DD
DD
267
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