mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 120

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mc68hc908rf2

Manufacturer Part Number
mc68hc908rf2
Description
M68hc08 Microcontrollers Microcontroller / Transmitter
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
10.5.1 Interrupts
Data Sheet
120
INTERRUPT
MODULE
I BIT
R/W
I BIT
R/W
IDB
IAB
IAB
IDB
INTERRUPT
MODULE
DUMMY
DUMMY
At the beginning of an interrupt, the CPU saves the CPU register contents on the
stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end
of an interrupt, the RTI instruction recovers the CPU register contents from the
stack so that normal processing can resume.
timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of
interrupt processing. The arbitration result is a constant that the CPU uses to
determine which vector to fetch. Once an interrupt is latched by the SIM, no other
interrupt can take precedence, regardless of priority, until the latched interrupt is
serviced (or the I bit is cleared). (See
SP – 4
SP
PC – 1[7:0]
Freescale Semiconductor, Inc.
Figure 10-9
CCR
For More Information On This Product,
SP – 1
SP – 3
Figure 10-9. Interrupt Recovery
PC – 1[15:8]
Figure 10-8
System Integration Module (SIM)
Go to: www.freescale.com
A
SP – 2
SP – 2
shows interrupt recovery timing.
X
X
.
SP – 3
SP – 1
Interrupt Entry
PC – 1 [15:8]
A
SP – 4
SP
Figure
PC – 1 [7:0]
CCR
VECT H
10-10.)
PC
Figure 10-8
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
MC68HC908RF2 — Rev. 4.0
shows interrupt entry
START ADDR
OPCODE
MOTOROLA

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