mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 91

• Manufacturer Part Number: mc68hc908rf2
• Description: M68hc08 Microcontrollers Microcontroller / Transmitter
• Manufacturer: Freescale Semiconductor, Inc

6.7.4 ICG DCO Divider Register
6.7.5 ICG DCO Stage Register
MC68HC908RF2 — Rev. 4.0
MOTOROLA
DDIV3–DDIV0 — ICG DCO Divider Control Bits
DSTG7–DSTG0 — ICG DCO Stage Control Bits
Address: $0039
Address: $003A
Reset:
Reset:
Read:
Read:
Write:
Write:
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally
controlled oscillator. Incrementing DDIV will add another divide-by-two,
doubling the period (halving the frequency). Decrementing has the opposite
effect. DDIV cannot be written when ICGON is set to prevent inadvertent
frequency shifting. When ICGON is set, DDIV is controlled by the digital loop
filter. The range of valid values for DDIV is from $0 to $9. Values of $A–$F are
interpreted the same as $9. Since the DCO is active during reset, reset has no
effect on DSTG and the value may vary.
These bits indicate the number of stages DSTG (above the minimum) in the
digitally controlled oscillator. The total number of stages is approximately equal
to $1FF, so changing DSTG from $00 to $FF will approximately double the
period. Incrementing DSTG will increase the period (decrease the frequency) by
0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG
cannot be written when ICGON is set to prevent inadvertent frequency shifting.
When ICGON is set, DSTG is controlled by the digital loop filter. Since the DCO
is active during reset, reset has no effect on DSTG and the value may vary.
Freescale Semiconductor, Inc.
For More Information On This Product,
DSTG7
Bit 7
Bit 7
R
R
0
Internal Clock Generator Module (ICG)
Figure 6-14. ICG DCO Divider Register (ICGDVR)
Figure 6-15. ICG DCO Stage Register (ICGDSR)
= Reserved
Go to: www.freescale.com
DSTG6
R
6
0
6
DSTG5
R
5
0
5
DSTG4
Unaffected by reset
R
4
0
4
U = Unaffected
Internal Clock Generator Module (ICG)
DSTG3
DDIV3
U
3
3
DSTG2
DDIV2
U
2
2
DSTG1
DDIV1
U
1
1
I/O Registers
Data Sheet
DSTG0
DDIV0
Bit 0
Bit 0
U
91