mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 208

• Manufacturer Part Number: mc68hc908sr12
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timebase Module (TBM)
12.6 Interrupts
Data Sheet
208
NOTE:
Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK — Timebase ACKnowledge
TBIE — Timebase Interrupt Enabled
TBON — Timebase Enabled
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2–TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request. The interrupt vector is defined in
Addresses.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
The TACK bit is a write-only bit and always reads as 0. Writing a logic
1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic
0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit
becomes set. Reset clears the TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off
to reduce power consumption when its function is not necessary. The
counter can be initialized by clearing and then setting this bit. Reset
clears the TBON bit.
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
Timebase Module (TBM)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Table 2-1 . Vector
Freescale Semiconductor