mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 229

• Manufacturer Part Number: mc68hc908sr12
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Address:
Figure 14-5. Analog Module Status and Control Register (AMSCR)
AMCDIV[1:0] — Analog Module Clock Divider Control Bits
OPIFR — Amplifier Ready Interrupt Flag Reset
OPIF — Amplifier Ready Interrupt Flag
Reset:
Read:
Write:
These read/write bits select the analog module input clock divider
value. The ADC clock, ADICLK, is divided by this value to obtain the
AMCLK. Reset clears the AMCDIV[1:0] bits.
Set AMCDIV1 and AMCDIV0 bits to zero for optimum analog module
performance.
Writing a logic 1 to this write-only bit clears the OPIF bit. OPIFR
always reads as a logic 0. Reset does not affect OPIFR.
This read-only bit is set when the output of the two-stage amplifier is
ready. A CPU interrupt request will be generated if the AMIEN bit is
also set. Reset clears OPIF bit.
1 = Clear OPIF bit
0 = No affect on OPIF bit
1 = Two-stage amplifier output is ready
0 = Two-stage amplifier output is not ready
AMCDIV1 AMCDIV0
$0010
Bit 7
0
Table 14-4. Analog Module Clock Divider Select
AMCDIV1
= Unimplemented
Analog Module
6
0
0
0
1
1
OPIFR
U
5
0
AMCDIV0
U = Unaffected
0
1
0
1
OPIF
4
0
3
0
0
Divider Value
Analog Module I/O Registers
16
2
4
8
DOF
2
0
CDIFR
U
1
0
Analog Module
Data Sheet
CDIF
Bit 0
0
229