mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 43

• Manufacturer Part Number: mc68hc05bs8
• Description: Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
• Manufacturer: Freescale Semiconductor, Inc

ICF - Input Capture Flag
This bit is set when a proper edge has been sensed by the input capture edge detector. It is
cleared by reading the TSR (with ICF set) followed by accessing the Input Capture register LSB
($0015).
OCF - Output Compare Flag
This bit is set when the Output Compare register matches the Counter register. It is cleared by
reading the TSR (with OCF set) and then accessing the Output Compare register LSB ($0017).
TOF - Timer Overflow Flag
This bit is set during the counter transition from $FFFF to $0000. It is cleared by reading the TSR
(with TOF set) followed by reading the counter LSB ($0019).
All three timer interrupt flags have corresponding enable bits (ICIE, OCIE, and TOIE) found in the
Timer Control register (TCR) at location $12. Reset clears all enable bits preventing an interrupt
from occurring. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents of $FFF6 and $FFF7.
Refer to section 6.1 for detailed description of the 16-bit Counter Timer.
5.2.2.5
There are two interrupt sources, TOF and RTIF bits of Multi-Function Timer Control and Status
Register. The interrupt service routine address is specified by the contents of memory location
$3FF4 and $3FF5.
CTOF - Timer Overflow
This bit is set when the 8-bit ripple counter overflows from $FF to $00; a timer overflow interrupt
will occur, if CTOFE is set. CTOF is cleared by writing a “0” to the bit.
MC68HC05BS8
CTimer Control and Status Register $0008
1 (set)
0 (clear) –
Core Timer Interrupts
–
CTimer counter overflow has occurred.
No CTimer counter overflow has occurred.
Address bit 7
RESETS AND INTERRUPTS
CTOF
RTIF CTOFE RTIE
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
RT1
bit 0
RT0
0000 0011
on reset
State
TPG
5