mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 86

• Manufacturer Part Number: mc68hc05bs8
• Description: Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
• Manufacturer: Freescale Semiconductor, Inc

9
9.10.4
This is a read/write register containing the line number for which the Vertical Sync Interrupt is to
be generated. Interrupt will be generated if VSIE bit is set, I bit in CCR is cleared, and the internal
line counter value matches the setting in this register after the Vsync pulse. The Vsync Interrupt
Vectors are at $3FF8 and $3FF9, and the interrupt latch is cleared by fetching the interrupt
vectors.
VSIE - Vsync Interrupt Enable
This bit enables and disables the Vsync interrupt.
LC6:0 - Line Count for Vsync Interrupt
These 7 bits store the line number for which the Vsync Interrupt will occur. The number is ranged
from 0 to 127.
9.10.5
This read/write register contains the line number for which the sampling pulse in SAM output to
be generated. The line number is ranged from 0 to 127. Sampling pulses are produced when there
is a Vsync pulse, or this register matches the horizontal line counter.
9.11
The sync processor accepts sync signals from the main computer; the signals can either be
separate Hsync and Vsync or composite sync through HSYNC input. Polarity correction is
performed before the sync signals go any further into the system. The sync pulse detection blocks
will continuously monitor the signal, to see if it is active. If the signal is not active, the circuit will
switch to output the internally generated clock signal. This will protect the circuits behind from
being damaged by an inactive signal.
9-10
1 (set)
0 (clear) –
ILCR
SPR
Interrupt Line Count Register (ILCR)
Sampling Pulse Register (SPR)
System Operation
–
Vsync interrupt enabled.
Vsync interrupt disabled.
Address bit 7
Address bit 7
$000E
$000F
SYNC SIGNAL PROCESSOR
VSIE
bit 6
bit 6
LC6
SP6
bit 5
bit 5
LC5
SP5
bit 4
bit 4
LC4
SP4
bit 3
bit 3
LC3
SP3
bit 2
bit 2
LC2
SP2
bit 1
bit 1
LC1
SP1
MC68HC05BS8
bit 0
bit 0
LC0
SP0
0000 0010
0000 0010
on reset
on reset
State
State
TPG