mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 69

• Manufacturer Part Number: mc68hc05bs8
• Description: Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
• Manufacturer: Freescale Semiconductor, Inc

SRW - Slave R/W Select
When MAAS is set, the R/W command bit of the calling address sent from the master is latched
into this SRW bit. By checking this bit, the CPU can then select slave transmit/receive mode by
configuring MTX bit of the M-Bus Control register.
MIF - M-Bus Interrupt
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
This bit must be cleared by software in the interrupt routine.
RXAK - Receive Acknowledge
If cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data
transmission on the bus. If set, no acknowledge signal has been detected at the 9th clock. This is
an active low status flag.
8.3.5
In master transmit mode, data written into this register is sent to the bus automatically, with the
most significant bit out first. In master receive mode, reading of this register initiates receiving of
the next byte data. In slave mode, the same function applies after it has been addressed.
MC68HC05BS8
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
2) A match of the calling address with its own specific address in slave mode -
3) A loss of bus arbitration - MAL set.
1 (set)
0 (clear) –
Address
$003D
clock - MCF set.
MAAS set.
M-Bus Data I/O Register (MDR)
–
–
–
bit 7
MD7
Read from slave, from calling master
Write to slave from calling master.
An M-Bus interrupt has occurred.
An M-Bus interrupt has not occurred.
No acknowledgment signal detected.
Acknowledgment signal detected after 8 bits data transmitted.
bit 6
MD6
bit 5
MD5
M-BUS SERIAL INTERFACE
bit 4
MD4
MD3
bit 3
bit 2
MD2
MD1
bit 1
bit 0
MD0
uuuu uuuu
on reset
State
TPG
8