mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 47

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.2.8 Halt Monitor
4.2.9 Spurious Interrupt Monitor
4.2.10 Software Watchdog
MC68331
USER’S MANUAL
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT) field in the sys-
tem protection control register (SYPCR). Table 4-2 shows the periods allowed.
The monitor does not check DSACK response on the external bus unless the CPU32
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.
The halt monitor responds to an assertion of the HALT signal on the internal bus. Refer
to 4.5.5.2 Double Bus Faults for more information. Halt monitor reset can be inhibited
by the halt monitor (HME) bit in SYPCR.
During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, recognizes the highest priority source, and then acquires a vector or re-
sponds to a request for autovectoring. The spurious interrupt monitor asserts the in-
ternal bus error signal (BERR) if no interrupt arbitration occurs during interrupt
exception processing. The assertion of BERR causes the CPU32 to load the spurious
interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 4.7 Interrupts for further information. For detailed infor-
mation about interrupt exception processing, refer to SECTION 5 CENTRAL PRO-
CESSING UNIT.
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
software service register SWSR on a periodic basis. If servicing does not take place,
the watchdog times out and asserts the reset signal.
Perform a software watchdog service sequence as follows:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
Freescale Semiconductor, Inc.
BMT
For More Information On This Product,
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01
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Table 4-2 Bus Monitor Period
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
Bus Monitor Time-Out Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
4-5
4