mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 10

• Manufacturer Part Number: mpc850de
• Description: Mpc850 Rev. A/b/c Communications Controller
• Manufacturer: Freescale Semiconductor, Inc

Layout Practices
For most applications P
between P
Solving equations (1) and (2) for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P
equations (1) and (2) iteratively for any value of T
5.1
Each V
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V
µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V
per capacitor lead. A four-layer board is recommended, employing two inner layers as V
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths
of six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
Special care should be taken to minimize the noise levels on the PLL supply pins.
Part VI Bus Signal Timing
Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10 pF.
Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
10
D
(at equilibrium) for a known T
P
K = P
D
CC
= K (T
D
pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each
Layout Practices
D
and T
•
(T
CC
A
J
J
+ 273 C)
is:
+ 273 C) +
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
I/O
< 0.3
MPC850 (Rev. A/B/C) Hardware Specifications
•
JA
A
P
. Using this value of K
INT
• P
D
and can be neglected. If P
CC
power supply should be bypassed to ground using at least four 0.1
(2)
(3)
A
.
CC
,
and GND should be kept to less than half an inch
the values of P
I/O
is neglected
D
and T
,
an approximate relationship
J
can be obtained by solving
CC
and GND planes.
MOTOROLA