mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 32

• Manufacturer Part Number: mpc850de
• Description: Mpc850 Rev. A/b/c Communications Controller
• Manufacturer: Freescale Semiconductor, Inc

1
Layout Practices
Figure 24 provides the PCMCIA access cycle timing for the external bus read.
32
Num
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
CLKOUT to ALE negate time
PCWE, IOWR negated to D[0–31]
invalid.
WAIT_B valid to CLKOUT rising edge.
CLKOUT rising edge to WAIT_B invalid.
1
Characteristic
Figure 24. PCMCIA Access Cycles Timing External Bus Read
MPC850 (Rev. A/B/C) Hardware Specifications
Table 8. PCMCIA Timing (continued)
1
1
3.00
8.00
2.00
Min
—
50MHz
13.00
Max
—
—
—
6.00
8.00
2.00
Min
—
66MHz
16.00
Max
—
—
—
4.00
8.00
2.00
Min
—
80 MHz
14.00
Max
—
—
—
FFACTOR Unit
0.250
0.250
MOTOROLA
—
—
ns
ns
ns
ns