mpc8379e Freescale Semiconductor, Inc, mpc8379e Datasheet - Page 25

• Manufacturer Part Number: mpc8379e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

1
Figure 7
8.2.1.2
Table 27
At recommended operating conditions with LV
Freescale Semiconductor
1
Input low voltage
Input high voltage
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t
appropriate letter: R (rise) or F (fall).
for inputs and t
transmit timing (MT) for the time t
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t
convention is used with the appropriate letter: R (rise) or F (fall).
The symbols used for timing specifications herein follow the pattern of t
The symbols used for timing specifications herein follow the pattern of t
shows the MII transmit AC timing diagram.
provides the MII receive AC timing specifications.
MII Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MRX
TXD[3:0]
TX_CLK
TX_EN
TX_ER
Parameter
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Table 27. MII Receive AC Timing Specifications
MTX
MRX
Figure 7. MII Transmit AC Timing Diagram
t
MTXH
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
DD
clock reference (K) going to the low (L) state or hold time. Note that, in general, the
MRDXKL
of 3.3 V ± 5%.
MTX
t
MTX
represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
symbolizes MII receive timing (GR) with respect to the time data input signals
t
Symbol
MRXH
t
t
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
V
V
IH
IL
/t
t
MTKHDX
MRX
t
MTXF
1
for outputs. For example, t
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
(first two letters of functional block)(signal)(state) (reference)(state)
10.0
10.0
Min
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
1.9
1.0
1.0
t
35
—
—
—
MTXR
Typical
400
40
—
—
—
—
—
—
—
MRDVKH
MTKHDX
MRX
clock reference (K) going
symbolizes MII receive
Max
0.7
4.0
4.0
symbolizes MII
65
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%
V
V
25