mpc8379e Freescale Semiconductor, Inc, mpc8379e Datasheet - Page 48

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mpc8379e

Manufacturer Part Number
mpc8379e
Description
Powerquicc Ii Pro Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Enhanced Secure Digital Host Controller (eSDHC)
11.2.2.2
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3
Table 43
Figure
48
At recommended operating conditions OV
SD_CLK clock frequency—high speed mode
SD_CLK clock cycle
SD_CLK clock frequency—identification mode
SD_CLK clock low time
SD_CLK clock high time
SD_CLK clock rise and fall times
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
SD_CLK delay within device
SD Card Input Setup
SD Card Input Hold
SD Card Output Valid
31.
provides the eSDHC AC timing specifications for high-speed mode as defined in
eSDHC AC Timing Specifications (High-Speed Mode)
Full-Speed Read Meeting Hold (Minimum Delay)
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Parameter
Table 43. eSDHC AC Timing Specifications for High-Speed Mode
t
CLK_DELAY
DD
= 3.3 V ± 165 mV.
+ t
OH
+ t
DATA_DELAY
t
INT_CLK_DLY
t
t
Symbol
t
t
t
t
t
SHSKHOV
SHSKHOX
t
SHSCKR/
SHSIVKH
SHSIXKH
f
SHSCKH
SHSCKF
t
SHSCKL
f
SHSCK
SFSCK
t
SIDCK
ODLY
t
ISU
t
IH
1
> t
SFSIXKH
Min
1.5
20
0
0
7
7
5
0
0
6
2
Max
400
50
14
3
4
Freescale Semiconductor
MHz
Unit
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 30
Notes
Eqn. 9
2
2
2
2
2
2
2
4
3
3
3
and

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