mpc880 Freescale Semiconductor, Inc, mpc880 Datasheet - Page 53

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mpc880

Manufacturer Part Number
mpc880
Description
Mpc885 Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1
2
3
4
Freescale Semiconductor
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
Num
78A
80A
83a
76
77
78
79
80
81
82
83
84
85
86
87
88
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
L1CLK edge to L1ST(1–4) valid
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
L1GR setup time
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4
2
Characteristic
4
4
Table 21. SI Timing (continued)
3
4
P + 10
P + 10
17.00
13.00
10.00
10.00
10.00
10.00
10.00
42.00
42.00
0.00
1.00
Min
All Frequencies
CPM Electrical Characteristics
SYNCCLK/2
16.00 or
45.00
45.00
45.00
55.00
55.00
42.00
30.00
Max
0.00
L1TCLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53

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