mpc880 Freescale Semiconductor, Inc, mpc880 Datasheet - Page 73
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mpc880
Manufacturer Part Number
mpc880
Description
Mpc885 Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC880.pdf
(88 pages)
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Figure 74
15.3
Table 36
Figure 75
15.4
Table 37
correctly with a maximum MDC frequency in excess of 2.5 MHz.
Freescale Semiconductor
Num
M10
M11
M12
M13
Num
M9
MII_TXD[3:0] (Outputs)
provides information on the MII async inputs signal timing.
provides information on the MII serial management channel signal timing. The FEC functions
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
shows the MII transmit signal timing diagram.
shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL minimum pulse width
MII_TX_CLK (Input)
RMII_REFCLK
MII_CRS, MII_COL
MII_TX_EN
MII_TX_ER
MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4
Table 37. MII Serial Management Channel Timing
Figure 74. MII Transmit Signal Timing Diagram
Figure 75. MII Async Inputs Timing Diagram
Table 36. MII Async Inputs Signal Timing
Characteristic
Characteristic
M5
M6
M7
M9
M8
Min
1.5
Min
—
10
0
0
Max
—
FEC Electrical Characteristics
Max
25
—
—
—
MII_TX_CLK period
Unit
Unit
ns
ns
ns
ns
73