mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 125

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mpc5644a

Manufacturer Part Number
mpc5644a
Description
Mpc5644a Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
3.17.10 FlexCAN system clock source
Freescale Semiconductor
1
2
3
SS timing specified at f
SRC = 0b00.
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
External Device Data Sample at
#
1
eQADC Data Sample at
F
Symbol
CAN_TH
1
2
3
FCK Falling Edge
FCK Rising Edge
Divides system clock source for FlexCAN engine by 1.
System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1.
Divides system clock source for FlexCAN engine by 2.
FlexCAN engine system clock threshold
SYS
System Frequency
Table 47. FlexCAN engine system clock divider threshold
= 80 MHz, V
SDO
FCK
SDS
<= F
SDI
> F
Table 48. FlexCAN engine system clock divider
CAN_TH
CAN_TH
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
DD
Figure 32. eQADC SSI timing
= 1.14 V to 1.32 V, V
Characteristic
4
5
2
2
1
1
1st (MSB)
Required SIU_SYSDIV[CAN_SRC] Value
3
3
6
7
DDEH
1st (MSB)
= 4.5 V to 5.5 V, T
8
2nd
2nd
0
1
1,2
2,3
25th
25th
A
= T
26th
L
to T
Value
100
Electrical characteristics
H
4
5
, and C
26th
L
= 50 pF with
MHz
Unit
125

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