mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 61

• Manufacturer Part Number: mpc5644a
• Description: Mpc5644a Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

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Microcontroller Reference Manual (SIU chapter) for details.
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For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or
secondary function or GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal.
The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO.
Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001,
A1 - 0b0010, A2 - 0b0100, A3 - 0b1000, or G - 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer
than four bits, remove the appropriate number of leading zeroes from these values.
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR
number. For example, PCR[190] refers to the SIU register named SIU_PCR190.
The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3
V to 5.0 V range (-10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).
See
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is
O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the
function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the
pin is enabled.
Output only.
When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.
Maximum frequency is 50 kHz.
Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing.
On 176 LQFP and 208 MAPBGA packages, this pin is tied low internally.
This signal name is used to support legacy naming.
For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA
specification to support analog input function.
Do not use VRC33 to drive external circuits.
VDDA0 and VDDA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called
VDDA.
VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VSSA.
VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support
legacy naming, however they should be considered as the same signal in this document.
VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present
to support legacy naming, however they should be considered as the same signal in this document.
VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present
to support legacy naming, however they should be considered as the same signal in this document.
The SIU_PCR219 register is unusual in that it controls pads for two separate device pins: GPIO[219] and MCKO. See the MPC5644A
VDDE2 and VDDE3 are shorted together in all production packages.
VDDE2 and VDDE3 are shorted together in all production packages.
Table 4
for details on pad types.