mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 10

• Manufacturer Part Number: mpc5554mzp80r2
• Description: Mpc5554 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
3.7
Power sequencing between the 1.5 V power supply and V
if using an external 1.5 V power supply with V
V
controller is not used. Refer to
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that V
before the POR signal negates. Refer to
VDD33.”
Although power sequencing is not required between V
not lead V
within specification. Higher spikes in the emitter current of the pass transistor occur if V
V
supply circuitry and the amount of board level capacitance.
10
1
2
3
4
5
6
7
8
9
10
RC33
DDSYN
Spec
V
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the V
transistor to the V
(less than 1 Ω). V
bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the V
I
Only available on devices that support -55
Refer to
Values are based on I
BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
VRCCTL
10
8
9
IL_S
must be powered up within the specified operating range, even if the on-chip voltage regulator
(Table
Voltage differential during power up such that:
V
reach the V
Absolute value of slew rate on power supply pins
Required gain at Tj:
I
DD
by more than these amounts. The value of that higher spike in current depends on the board power
is measured at the following conditions: V
Table 1
DD33
Power-Up/Down Sequencing
DDSYN
– 55
– 40
25
150
÷
9, Spec15) is guaranteed to scale with V
o
I
VRCCTL
can lag V
o
C
o
o
C
C
C
for the maximum operating frequency.
RCCTL
DD
7
by more than 600 mV or lag by more than 100 mV for the V
POR33
package signals must have a maximum of 100 nH inductance and minimal resistance
(@ f
DD
must have a nominal 1 μF phase compensation capacitor to ground. V
DDSYN
RCCTL
from high-use applications as explained in the I
and V
sys
Table 6. VRC/POR Electrical Specifications (continued)
= f
or V
package signal to the base of the external pass transistor and between the emitter of the pass
POR5
MAX
Characteristic
DDEH6
Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),”
)
MPC5554 Microcontroller Data Sheet, Rev. 2.0
5, 6, 8, 9
minimums respectively.
DD33
, before V
o
C.
must reach a certain voltage where the values are read as ones
Section 3.7.1, “Input Value of Pins During POR Dependent on
DD
DDSYN
DDEH6
= 1.35 V, V
RC33
and V
down to V
tied to ground (GND). To avoid power-sequencing,
RC33
DDEH6
RC33
DDSYN
= 3.1 V, V
and V
POR5
DD
.
or the RESET power supplies is required
Electrical Specification.
DDSYN
V
VRCCTL
DD
Symbol
DD33_LAG
BETA
supply signals.
10
during power up, V
= 2.2 V.
RC
DD
stage turn-on to operate
must have a 20 μF (nominal)
105
85
Freescale Semiconductor
Min
70
70
—
—
10
10
RC33
and
DD
Max
leads or lags
500
1.0
÷
50
—
—
—
RC33
I
VRCCTL
must
Units
V/ms
mA
—
—
—
V
).