mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 2

• Manufacturer Part Number: mpc5554mzp80r2
• Description: Mpc5554 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Overview
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5554 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the
32-kilobytes (KB) unified cache. The next level in the hierarchy contains the 64-KB on-chip internal
SRAM and 2-megabytes (MB) internal flash memory. The internal SRAM and flash memory can hold
instructions and data. The external bus interface has been designed to support most of the standard
memories used with the MPC5xx family.
The complex input/output timer functions of the MPC5500 family are performed by two enhanced time
processor unit (eTPU) engines. Each eTPU engine controls hardware channels, providing a total of 64
hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double-action
hardware channels, variable number of parameters per channel, angle clock hardware, and additional
control and arithmetic instructions. The eTPU can be programmed using a high-level programming
language.
The less complex timer functions of the MPC5500 family are performed by the enhanced modular
input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action,
double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control
capabilities include edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU of the MPC5554 has an on-chip 40-channel enhanced queued dual analog-to-digital converter
(eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides
multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal
multiplexing.
MPC5554 Microcontroller Data Sheet, Rev. 2.0
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Freescale Semiconductor