gc80c520g CORERIVER Semiconductor, gc80c520g Datasheet - Page 19

• Manufacturer Part Number: gc80c520g
• Description: Eprom / Rom / Romless Based 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

ADCSEL (E2h) : ADC Input Select Register
P0SEL (E4h) : P0 Pull-up Control Register
P0 (80h) : PORT0 Register
P0SEL.7 P0SEL.6 P0SEL.5 P0SEL.4 P0SEL.3 P0SEL.2 P0SEL.1 P0SEL.0
R/W(0) R/W(0) R/W(0)
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
ADIV2
6.5. I/O Ports : PORT0[7:0]
P0.7
Open-Drain output at default condition (Intel 8052 compatible).
Only the P0.0 pin is available for analog input (ADC input channel 0).
During accesses to external memory, the P0 SFR will be automatically set to “FFh”.
Internal pull-up resistors are switched on/off by changing the value of the P0SEL SFR.
If the Port is used as ADC Function, ADC_EN Bit must be Set. Then Internal pull-up become off.
Read-Modify-Write instructions do not read port pin but the port SFR.
PORT0 Description
ADC0 : 1 = ADC0 input enable & digital input disable at P0.0.
P0SEL[7:0] :
ANL
ADIV1
P0.6
/
ORL
ADIV0
P0.5
Pull-up resistor enable
0 = Pull-up resistor ON
1 = Pull-up resistor Off when ADC_EN(ADNCON[7]) = 1
PORT0 Pull-up resistor is
/
XRL
P0.4
/
-
JBC
/
R/W(0) R/W(0) R/W(0) R/W(0)
ADC3
P0.3
CPL
/
INC
ADC2
P0.2
OFF
/
DEC
after reset.
ADC1
P0.1
/
DJNZ
ADC0
P0.0
/
MOV PX.Y, C
CPU BUS
/
External Address/Data
External Access
CLR PX.Y
ADC Block Input
P0.0
SFR
Digital Input
/
QB
SETB PX.Y
Q
MiDAS1.0 Family
ADC0
Pull-
up
P0SEL.0
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