gc41c501g1-so24i CORERIVER Semiconductor, gc41c501g1-so24i Datasheet
gc41c501g1-so24i
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gc41c501g1-so24i Summary of contents
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... Brief Manual of ATOM1.1 Family 4-bit Microcontrollers with Reduced 8051 Architecture CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time. CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a service through its homepage ...
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Contents 1. Product Overview 2. Features 3. Block Diagram 4. Pin Configurations 5. Pin Descriptions 6. Function Descriptions CPU Descriptions - Memory Organization - SFR Map and Description - Instruction Set Summary - CPU Timing Peripheral Descriptions - I/O Ports ...
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... Product (byte) (byte) (byte) GC49C501G1-SO24I - 1K (128) GC49C501G1-SJ20I - 1K (128) GC41C501G1-SO24I 1K - GC41C501G1-SJ20I User may use part of program area (128 bytes) as EEPROM, which can be modified by IAP function during S/W operation. * Max. operating frequency of ATOM1.1 family is 5 MHz when VDD is less than 2.7 V. RAM Volt Freq. T/C Serial ...
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Features CPU 4-bit reduced 8051 architecture Continuous program addressing, not paged. 51 instructions including push, pop and logic inst. Instruction cycle : F /6 SYS Multi-level subroutine nesting with RAM based stack. On-chip Memories FLASH : 1024 bytes (including ...
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Features Power Consumption Stop mode : ＜0.1uA (Typ (Max.) at 5.0V Normal mode : 400 uA (Typ.) at 2.0V, F Operating frequency vs. voltage Max MHz (2.7 V ≤ V OSC Max. ...
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Block Diagram (24-PIN) Instruction Decoder (IR) 4 WDT POR/LVD RING OSC. OSC P4[3:2] P0[3:0] P1[3:0] P2[3:0] P3[3:0] RomAddr( FLASH 1K Bytes RomOut( RomOut( ) CPU BUS( Data Address ALU (SPH,SPL, (C, ACC) DPH, DPL) DPL ...
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Block Diagram (20-PIN) Instruction Decoder (IR) 4 WDT POR/LVD RING OSC. OSC P0[3:0] P1[1:0] P2[3:0] P3[3:0] RomAddr( FLASH 1K Bytes RomOut( RomOut( ) CPU BUS( Data Address ALU (SPH,SPL, (C, ACC) DPH, DPL) DPL 4 ...
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Pin Configurations REM P0.0 P2.0/SCLK 4 17 P0.1 P2.1/SDAT P2.2 P2.3 P0 P3 P3.1 ...
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Pin Description (20-pin/24-pin) Symbol Direction V Power Power Supply DD V Power Ground SS REM Output Output for IR LED drive Transistor. The transistor is n-channel device. TV Power Ground for IR LED drive Transistor SS XI Input Input ...
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Memory Organization Address Space Program memory : 1K Bytes. Continuously addressed by Byte. Indirect data memory : 64 Nibbles. Bit accessible. Special function registers : 16 Registers. Directly addressed. Indirect function flags : 16 bits. Bit position is selected ...
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SFR Brief Description Register Address P0 00H Port 0 output register. P4 01H Port 4 output register. DPL 02H The low nibble of data pointer (DPTR). DPH 03H The high nibble of data pointer (DPTR). P1 04H Port 1 ...
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Indirect Function Flag (IFF) Description Indirect Function Flag (IFF) Write only, access using the instructions: MOV L, #n, SETB @L, CLR @L The individual set/clear of ports is available only if the package type supports corresponding parallel port. Flag ...
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Instruction Set Summary (1/2) Refer to Appendix A (Instruction Set) for more details. Type Instruction ADD A, #data INC A DEC A ADD A, @DP Arithmetic ADDC A, @DP SUB A, @DP INC @DP DEC @DP CLR A CPL ...
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Instruction Set Summary (2/2) Refer to Appendix A (Instruction Set) for more details. Type Instruction CJNE @DP, #data, rel CJNE L, #data, rel CJNE A, dir, rel CJNE A, @DP, rel CJLE A, @DP, rel CJNE A, #data, rel ...
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CPU Timing CPU takes 6 clocks for a machine cycle. Any instruction except branch instructions completes in one machine cycle. All branch instruction consumes 2 machine cycles whether the branch is taken or not. The state of SFR, I/O ...
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I/O Ports : PORT0 ~ PORT4 All ports are initialized asynchronously on power-up. Pull-up enable and input by default (reset). Open drain active low output. P2[3:0] may be configured as push-pull output port. CPU always write to SFR register, ...
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I/O Ports : Mapping IOCFG This SFR is initialized to default state only by power-on- reset. Only the P2OEN bit is cleared by other resets. IOCFG (0Eh) : I/O Port Configuration Register IOMAP1 IOMAP0 P2OEN R/W(0) R/W(0) R/W(0) P2OEN ...
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I/O Ports : I/O Mapping User may select I/O port mapping by setting IOCFG SFR. The functionality of each I/O pins is the same for any mapping. This configuration option is useful when the pin-to-pin compatibility with existing devices ...
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Clock Configuration Two System Clock Sources : Internal Ring OSC. or External Resonator/Crystal Default System Clock is Ring OSC. When user changes the clock source (XT/RG bit), internal reset is generated. Internal reset does not affect CKCFG. The configuration ...
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Clock Configuration: Guideline Resonator / Crystal Oscillator ATOM XO XI Oscillator Module ATOM XO XI OSC Oscillator Module Preliminary Internal Ring Oscillator ATOM XO Ring XI OSC. RC Oscillator [20] ATOM1.0 Family ...
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Carrier Frequency Generation Support 7 types of carrier frequency. REMC (05h) : The REM Output Control Register. REME PG2 PG1 R/W(0) R/W(0) R/W(0) PG[2:0] : Carrier Frequency Selection. REME : REM Output Enable. Pulse F SYS Generator PG2 PG1 ...
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Carrier Frequency Generation Waveform Example REM output is the inverse of REMI* Since the IR. LED drive transistor in ATOM is a N-Type, IR. LED is turned on when REMI* is high. System Clock (F ) SYS REME REMI* ...
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POR & LVD : Power-On Reset On-chip power-on reset is a logical OR of RC-POR and LVD-POR RC-POR operates when the rising time of power ( short. DD On-chip LVD Provides power-on reset when the rising time ...
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POR & LVD : Condition for power notch Power-on-reset is independent of power-rising slope. Voltage Power slope = 1 VDD Power slope = 0. The cases of reset generation by VDD ...
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WDT (Watchdog Timer) WDT Free running counter which resets CPU every 2 system clock cycles. Although the counter length is fixed, WDT overflow period may vary according to the current frequency of system clock. WDT is halt in STOP ...
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Reset Circuit Reset Sources Power-on Reset (POR) when Power-Up. Power-fail Reset STOP mode Wake-up by changes in input port P0 or P1. WDT Overflow for abnormal condition or SLEEP mode. Clock source change (State change of CKCFG[3]). Device Reset ...
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Power Management : 3 Modes Active Mode CPU and peripheral are running. Sleep Mode Only WDT is running. I/O ports hold the state before sleep mode. Wake-up by WDT overflow. The longest period of WDT overflow is 1.1 second ...
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In Application Programming (IAP) In Application Programming User S/W can read or modify specific regions of FLASH with IAP function during operation. The EEP0/1 regions may be used as program memory or data memory. CPU is halt during IAP ...
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In Application Programming (IAP) Electrical Characteristic of IAP Note that the program time depends on the configuration of system clock frequency. If the system clock frequency is out of IAP range, user need to change F before and after ...
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Absolute Maximum Ratings Absolute Maximum Ratings Symbol Parameter V DC supply voltage input voltage output voltage OUT I DC output high current output low current OL T Storage temperature STG ...
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DC Characteristics * - + 1.8V ~ 5.5V unless otherwise specified. DD Parameter Symbol Input Low Voltage V P0, P1 ,P2 ,P3 IL1 Input high Voltage V P0, P1 ...
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AC Characteristics * unless otherwise specified. TBD = To Be Determined. Parameter Symbol Oscillator Frequency F OSC (Internal Clock) Oscillator Frequency F XI, XO OSC (External Clock) System Frequency F ...
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Package Dimensions pins Seating Plane pins Seating Plane ...
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Product Numbering System General Core MCU Series Core Type bits bits bits bits ROM Type 0 ...
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Supporting tools MDS (Microprocessor Development System) Easy-to-Use GUI Application System On-board Implemented Various Application Various Sample Test Program Code Generation Tools Assembler & Linker for DOS & Windows User-Friendly User-Friendly Development Development Environment Environment ROM Writer Optional Parallel/Serial Program ...
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Appendix A : Instruction Set (1/19) Abbreviations and Symbols Symbol Description PC The program counter. A The accumulator register (ACC). C The carry flag. The stack pointer register. SP Concatenation of SPH and SPL. (DP) The contents of DPTR. The ...
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Appendix A : Instruction Set (2/19) OPCODE Map SETB PUSH POP 0 NOP CLR C INC A ADD A, #data 2 MOV L, #data 3 MOV H, #data 4 MOVI ...
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Appendix A : Instruction Set (3/19) ADD A, #data Binary Code 0001 dddd Description Adds the 4-bit data to the Accumulator. The result is stored in Accumulator. When adding unsigned integers, the carry flag indicates an overflow. Operation (A) ← ...
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Appendix A : Instruction Set (4/19) ANL A, @DP Binary Code 0000 1100 Description ANL performs the bitwise logical-AND operation between the indirect data memory and ACC. The result is stored in Accumulator. Operation (A) ← (A) & M[DP] Carry ...
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Appendix A : Instruction Set (5/19) CJLE A, @DP, rel Binary Code 1001 0011 Description Compares the contents of ACC and the indirect memory, and branches if the value in ACC is less than or equal to that in memory. ...
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Appendix A : Instruction Set (6/19) CJNE A, #data, rel Binary Code 1100 dddd Description Compares the contents of Accumulator and data in four low-order bits of opcode, and branches if their values are not equal. The branch destination is ...
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Appendix A : Instruction Set (7/19) CJNE A, dir, rel Binary Code 1101 dddd Description Compares the contents of ACC and that of SFR addressed by four low-order bits of opcode, and branches if their values are not equal. The ...
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Appendix A : Instruction Set (8/19) CLR @L Binary Code 1000 0110 Description Clears the indirect function flag addressed by DPL. Operation F[L] ← 0 Carry Flag Not affected. Bytes 1 Cycles 1 Example ; Assumes P2 contains 0xF. MOV ...
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Appendix A : Instruction Set (9/19) CPL A Binary Code 0000 1010 Description Complements the contents of ACC. Operation (A) ← ~(A) Carry Flag Not affected. Bytes 1 Cycles 1 Example MOV A, P0 CPL A DEC @DP Binary Code ...
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Appendix A : Instruction Set (10/19) DJNZ A, rel Binary Code 1001 0001 Description Decrements the contents of ACC, and branches if the result is not zero. The branch destination is computed by adding the signed relative-displacement in the second ...
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Appendix A : Instruction Set (11/19) INC DPTR Binary Code 0000 0100 Description Increments the data pointer. Operation (DP) ← (DP Carry Flag Not affected. Bytes 1 Cycles 1 Example ; Assumes all bits of DPTR is 1. ...
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Appendix A : Instruction Set (12/19) JC rel Binary Code 1001 0111 Description Branches if the carry flag is 1. The branch destination is computed by adding the signed relative-displacement in the second byte of the instruction to the PC, ...
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Appendix A : Instruction Set (13/19) JNB bit, rel Binary Code 1001 10bb Description Branches if the bit in data memory is 0. The address of memory is given by DPTR and bit position is given by two least significant ...
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Appendix A : Instruction Set (14/19) MOV @DP, A Binary Code 1000 0011 Description The contents of ACC is copied to data memory whose address is given by DPTR. Operation M[DP] ← (A) Carry Flag Not affected. Bytes 1 Cycles ...
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Appendix A : Instruction Set (15/19) MOV H, #data Binary Code 0011 dddd Description Sets DPH with the data given in four low-order bits of opcode. Operation (H) ← #data Carry Flag Not affected. Bytes 1 Cycles 1 Example MOV ...
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Appendix A : Instruction Set (16/19) MOVD @DP, A Binary Code 1000 0101 Description The contents of ACC is copied to data memory whose address is given by DPTR. After that the data pointer is decremented. Operation M[DP] ← (A) ...
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Appendix A : Instruction Set (17/19) NOP Binary Code 0000 0000 Description No operation. Just fetches the next instruction. Operation (PC) ← (PC Carry Flag Not affected. Bytes 1 Cycles 1 Example NOP POP A Binary Code 0000 ...
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Appendix A : Instruction Set (18/19) RET Binary Code 1001 0000 Description Returns from subroutine. The stack pointer is decremented three times. Operation (PC ) ← M[SP] 11-8 (SP) ← (SP (PC ) ← M[SP] 7-4 (SP) ← ...
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Appendix A : Instruction Set (19/19) SETB bit Binary Code 1000 11bb Description Sets a bit in data memory indirectly addressed by DPTR. The bit position is obtained at the least significant two bits of opcode. Operation M[DP].bit ← 1 ...
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Appendix B : SFR Description [00h ~ 07h] [How to Read a SFR Descriptions] Yellow Color : Bit Addressable SFR Address White Color : Byte Addressable P2 (08h) : Port 2 Output Register P2.3 P2.2 P2.1 R/W(1) R/W(1) R/W(1) R ...
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Appendix B : SFR Description [08h ~ 0Dh] P2 (08h) : Port 2 Output Register P2.3 P2.2 P2.1 R/W(1) R/W(1) R/W(1) IAPCON (09h) : IAP Control Register RGS1 RGS0 OPS1 R/W(0) R/W(0) R/W(0) RGS[1:0] : Select IAP region. [0,0] : ...
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Appendix B : SFR Description [0Eh ~ 0Fh] IOCFG (0Eh) : I/O Port Configuration Register IOMAP1 IOMAP0 P2OEN R/W(0) R/W(0) R/W(0) P2OEN : Configure P2 as push-pull output port. IOMAP [1:0] : Configure I/O ports mapping. [0,0] : Default. [0,1] ...
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Appendix C : Update History V1.0 Initial Release Preliminary [58] ATOM1.0 Family ...