gc80c590ae CORERIVER Semiconductor, gc80c590ae Datasheet
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... Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. The CORERIVER Semiconductor products listed in this document are intended for usage in general electronics applications. These CORERIVER Semiconductor products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ...
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Contents 1. Product Overview 2. Features 3. Block Diagram 4. Pin Configurations 5. Pin Descriptions 6. Function Descriptions CPU Descriptions - Memory Organization - SFR Map and Description - Instruction Set Summary - CPU Timing - IO configuration Peripheral Descriptions ...
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Product Overviews CORERIVER’s MiDAS2.0 Family is a group of fast 80C52 compatible microcontrollers The instruction execution of MiDAS2.0 is max. traditional 80C52. 1 Machine cycle = 4 clocks vs. 12 clocks Additional peripherals of MiDAS2.0 Family: 10 bit ADC ...
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... Product Overview A. MiDAS2.0 Family - GC80C590AE Series (ISP Flash MCU) EEPROM Mask-ROM Flash Product (byte) (byte) (byte) GC89C591A0-TQ100I GC89C591A0-P64I GC89C591A0-LQ64I 2K - 62K GC89C591A0-TQ64I GC89C591A0-PL44I GC89C591A0-MQ44I GC81C591A0-TQ100I GC81C591A0-P64I GC81C591A0-LQ64I 2K 62K GC81C591A0-TQ64I GC81C591A0-PL44I GC81C591A0-MQ44I GC89C541A0-TQ100I GC89C541A0-P64I GC89C541A0-LQ64I 2K - 14K GC89C541A0-TQ64I GC89C541A0-PL44I GC89C541A0-MQ44I GC81C541A0-TQ100I GC81C541A0-P64I GC81C541A0-LQ64I 2K 14K ...
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... Product Overview A. MiDAS2.0 Family - GC80C590AE Series (ISP Flash MCU) EEPROM Mask-ROM Flash Product (byte) (byte) (byte) GC89C581A0-TQ100I GC89C581A0-P64I GC89C581A0-LQ64I 2K - 30K GC89C581A0-TQ64I GC89C581A0-PL44I GC89C581A0-MQ44I GC81C581A0-TQ100I GC81C581A0-P64I GC81C581A0-LQ64I 2K 30K GC81C581A0-TQ64I GC81C581A0-PL44I GC81C581A0-MQ44I Semiconductor Co., Ltd. (Cont’d) RAM Volt Freq. T/C Serial WDT (Byte) (V) (MHz) ...
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Features CPU 8-bit turbo 80C52 architecture 4 cycles/1 machine cycle Pin/instruction level compatible with Intel 80C52 16/32/62 KBytes on-chip FLASH ROM ISP by serial interface IAP and virtual EEPROM for data (2KByte) On-chip H/W debugging engine for ICE. 2 ...
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Features (Cont’d) Wake-up from power-down mode External reset External interrupt 0/1 WDT interrupt or reset Reset scheme On-chip power-on-reset External reset Low voltage detector reset Watchdog timer reset if enabled Internal power stabilization counter Extends power on reset up ...
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Block Diagram RESET XTAL1 XTAL2 RESET External Osc. Internal Ring Osc. WDT TURBO 80C52 CORE LVD ALE PSEN VDD Semiconductor Co., Ltd. P3[7:0] P2[7:0] Port Controller ADC Interrupt Controller CPU BUS Timer0 RAM FLASH EEPROM Timer1 ...
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Block Diagram (Cont’d) RESET XTAL1 XTAL2 RESET External Osc. Internal Ring Osc. WDT TURBO 80C52 CORE LVD ALE PSEN VDD Semiconductor Co., Ltd. P5[7:0] P4[7:0] Port Controller ADC Interrupt Controller CPU BUS Timer0 RAM FLASH EEPROM ...
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Block Diagram (Cont’d) RESET XTAL1 XTAL2 RESET External Osc. Internal Ring Osc. WDT TURBO 80C52 CORE LVD ALE PSEN VDD Semiconductor Co., Ltd. P9[7:0] P8[7:0] P7[5:0] P6[7:0] P5[7:0] P4[7:0] Port Controller ADC Interrupt Controller CPU BUS ...
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Pin Configurations : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output ADC5 / INT3 / P1.5 7 ADC6 / INT4 / P1.6 8 ADC7 / ...
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Pin Configurations T2EX / P1.1 64 P1 ADC0 / P4.0 61 P0.0 / AD0 / 4 60 ADC1 / P4.1 5 P0.1 / AD1 / 59 ADC2 ...
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Pin Configurations : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output) 100 ADC5 / P4.5 1 ADC6 / P4.6 2 ADC7 / P4.7 3 INT2 / ...
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Pin Descriptions Symbol Direction V Input Power Supply DD AV Input Reference Voltage for ADC DD V Input Ground SS AV Input Reference Ground for ADC SS RESET Input External Reset XTAL1 Input Input to the inverting oscillator amplifier ...
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Pin Descriptions Symbol Direction An 8-bit Quasi-bidirectional I/O port. 5V Tolerant Input. 64/80/100 pins Package : General I/O. • P1.0 • P1.1 • P1.4 • P1.5 • P1.6 • P1.7 An 8-bit Quasi-bidirectional I/O port. 3.3V Tolerant Input. 44 ...
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Pin Descriptions Symbol Direction An 8-bit Quasi-bidirectional I/O port. 5V Tolerant Input. Note that the output is fully driven (push-pull) when P2 drives the high byte of address to access external RAM or PCA0 drives output signals (C0EXn). P2[7:0] ...
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Pin Descriptions Symbol Direction 3.3V Operation Programmable I/O Port used as Schmitt Trigger Input or Push-pull Output. P5[7:0] Input/Output An Internal Pull-up Resistor is switched on/off by S/W. After Reset, this port will be configured as Input and the ...
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Memory Organization F7FFh Internal FLASH 30h 0000h 20h 18h Interrupt Vector 10h 08h 00h [ On-chip Program Memory ] (Read/Write with IAP) Semiconductor Co., Ltd. Refer to Family Table FFh Internal RAM (Only 7Fh Indirect) 80h ...
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SFR (Special Function Register) Map Refer to Family Table F8h FFh F0h Internal SFR RAM E8h (Only (Only Direct) Indirect) E0h 80h D8h Internal D0h RAM (Indirect or C8h Direct) C0h 00h B8h B0h A8h A0h 98h 90h 88h ...
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SFR Brief Description 80C52 SFR Registers Register Name ACC Accumulator B B Register PSW Program Status Word SP Stack Pointer DPTR Data Pointer (2 bytes) DPL Low byte DPH High byte P0 Port 0 P1 Port 1 P2 Port ...
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SFR Brief Description Newly added SFR Registers in MiDAS2.0 Family (Cont’d) Register Name PMR Power Management EXIF External Interrupt Flag CKCON Clock Control STATUS Crystal Status OSCICN Internal RING Oscillator Control IOCFG I/O Configuration C0L Low Byte of PCA0 ...
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Instruction Set Summary Refer to Appendix A (Instruction Set) for more details. Type Instruction Addition ADD Addition with Carry ADDC Subtraction with Borrow SUBB Increment INC Arithmetic Decrement DEC Multiply MUL Divide DIV Decimal Adjust DA AND ANL OR ...
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CPU Timing Comparative timing of the MiDAS2.0 family and Intel 80C52 XTAL1 IR ALE CORERIVER PSEN MiDAS2.0 PORT0 INST0 PORT2 ADDH_0 XTAL1 IR Intel 80C52 ALE PSEN PORT0 ADDL_12 PORT2 ADDH_12 Semiconductor Co., Ltd. INST0 INST1 ADDL_1 INST1 ADDL_2 ...
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CPU Timing : MOVX Write Timing XTAL1 IR INST0 INST1 ALE PSEN WR PORT0 INST1 ADDL_1 MOVX PORT2 ADDH_0 ADDH_1 Semiconductor Co., Ltd. 1st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle ...
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CPU Timing : MOVX Read Timing XTAL1 IR INST0 INST1 ALE PSEN RD PORT0 INST1 ADDL_1 MOVX PORT2 ADDH_0 ADDH_1 Semiconductor Co., Ltd. 1st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle ...
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CPU Timing : Instruction Execution Time The Fastest instruction execution in the world MiDAS2.0 Instruction (CORERIVER) MUL AB 12 clocks DIV AB MOVC A, @A+PC 8 clocks MOVC A, @A+DPTR 8 clocks JMP @A+DPTR RET 8 clocks RETI 4 ...
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I/O Ports : PORT0[7:0] 5V tolerant input and open-drain output in default condition (Intel 8052 compatible). The output is fully driven (push-pull) when P0 drives address/data to access external RAM or PCA1 drives output signals (C1EXn). During access to ...
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I/O Ports : PORT1[7:0] An 8-bit 5V tolerant input quasi-bidirectional port (Intel 8052 compatible). Read-Modify-Write instructions do not read port pin but read SFR register. ANL / OPL / XRL / JBC / CPL An available alternative input functions ...
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I/O Ports : PORT1[7:0] 3.3V operation A port used as quasi-bidirectional I/O (Intel 8052 compatible) or ADC input. Read-Modify-Write instructions do not read port pin but read SFR register. ANL / OPL / XRL / JBC / CPL Available ...
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I/O Ports : PORT2[7:0] An 8-bit 5V tolerant input quasi-bidirectional port (Intel 8052 compatible). The output is fully driven (push-pull) when P2 drives the high byte of address to access external RAM or PCA0 drives output signals (C0EXn). Read-Modify-Write ...
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I/O Ports : PORT3[7:0] An 8-bit 5V tolerant input quasi-bidirectional port (Intel 8052 compatible). Read-Modify-Write instructions do not read port pin but read SFR register. ANL / OPL / XRL / JBC / CPL The available alternative input function ...
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I/O Ports : PORT4[7:0] An 8-bit 3.3V operation quasi-bidirectional port (Intel 8052 compatible). Used as ADC input channel or Digital Input/Output. Read-Modify-Write instructions do not read port pin but read SFR register. ANL / OPL / XRL / JBC ...
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I/O Ports : PORT5[7:0] 3.3V operation and push-pull output. A pull-up is switched on/off by changing the value of the P5UP register. I/O direction is determined by the value of the P5DIR register. PORT 5 Description P5DIR (BAh) : ...
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I/O Ports : PORT6[7:0] 3.3V operation and push-pull output. A pull-up is switched on/off by changing the value of the P6UP register. I/O direction is determined by the value of the P6DIR register. PORT 6 Description P6DIR (BBh) : ...
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I/O Ports : PORT7[7:0] 3.3V operation and push-pull output. A pull-up is switched on/off by changing the value of the P7UP register. I/O direction is determined by the value of the P7DIR register. PORT 7 Description P7DIR (BCh) : ...
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I/O Ports : PORT8[7:0] 3.3V operation and push-pull output. A pull-up is switched on/off by changing the value of the P8UP register. I/O direction is determined by the value of the P8DIR register. PORT 8 Description P8DIR (BDh) : ...
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I/O Ports : PORT9[7:0] 3.3V operation and push-pull output. A pull-up is switched on/off by changing the value of the P9UP register. I/O direction is determined by the value of the P9DIR register. PORT 9 Description P9DIR (BEh) : ...
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I/O Ports : PORT Configuration MiDAS2.0 family provides a dedicated address register for If configured so, the AUXAD register provides the high byte of address for Then, the PORT2 can be used exclusively as general purpose I/O or PCA ...
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LVD (Low Voltage Detector) On-chip power-on reset : 2.0V On-chip power-fail reset : 2.0V Optional power-fail interrupt : 2.7V After POR pulse is off, the internal power stabilization counter starts to run, which lengthens power-up reset to 50ms. Flag ...
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WDT (Watch Dog Timer) Detects software upset due to external noise or other causes Allows an automatic recovery using WDT interrupt If enabled, WDT interrupt or WDT reset makes MCU wake up from stop mode. Watchdog Time-out Values (CKCON[7:6]) ...
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Timer/Counter : Timer 0/1 Compatible with traditional 80C52 Timer/Counter function Time base is selectable by S clocks or 12 clocks Mode Mode 0 Mode 1 Mode 2 Timer (M1,M0=00) (M1,M0=01) (M1,M0=10) 8-bit T/C Timer0 13-bit T/C 16-bit ...
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Timer/Counter : OSC 1/ 1/4 CONTROL C/T=0 TxM TLx (5bits) (8bits) Tx PIN C/T=1 TRx GATE INTx PIN [Mode 0] OSC 1/ 1/4 CONTROL C/T=0 TxM TLx (8bits) Tx PIN C/T=1 TRx GATE INTx PIN ...
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Timer/Counter : Timer 2 Compatible with traditional 80C52 Timer/Counter 2 function Up or down counting selectable by a software Time base is selectable by S clocks or 12 clocks 16-bit Timer/Counter 1. 16-bit Auto-reload With Automatic Reload ...
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Timer/Counter : Timer 2 Mode Description OSC 1/ 1/4 CONTROL C/T2=0 T2M TL2 TH2 T2 PIN C/T2=1 TR2 Capture Transition RCAP2L RCAP2H Detection CONTROL T2EX PIN EXF2 EXEN2 [Capture Mode] (Down Counting Reload Value) 0FFh 0FFh OSC ...
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Timer/Counter : Timer 2 Mode Description OSC 1/2 CONTROL C/T2=0 TL2 TH2 T2 PIN C/T2=1 TR2 RCAP2L RCAP2H Transition Detection CONTROL T2EX (P1.1) EXEN2 [Baud Rate Generator Mode] Semiconductor Co., Ltd. Timer 1 Overflow 1 SMOD1 1 ...
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UART (UART0/UART1) Function-level compatible with traditional 80C52 UART. Automatic address recognition : Multi processor communication. The SFR name for UART0 is the same as the legacy UART. Data Size Mode 0 8 bits 8 data bits 1/4 x Oscillator ...
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UART : Automatic Address Recognition Example Slave 1: SADDR = 11110001 SADEN = 11111010 GIVEN = 11110X0X Slave 2: SADDR = 11110011 SADEN = 11111001 GIVEN = 11110XX1 • A master can selectively communicate with groups of slaves by ...
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UART : UART1 SFRs SCON1 (B1h) : Serial Port Control Register for UART1 SM0 SM1 SM2 REN TB8 RB8 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) SM0, SM1 : Serial Port Operating Mode Selection [0,0] : Mode 0. ...
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UART : Baud Rate Example Serial Port Mode 0 Oscillator Frequency Baudrate = 4 Serial Port Mode 2 2 SMOD1 Baudrate = X 32 EX) Using Timer 1 to Generate Baudrates 2 SMOD1 Mode 1 & 3 Baudrate = ...
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UART : Mode 0 Function Write to SBUF OSC Serial Port Interrupt REN RI Load SBUF Read SBUF Semiconductor Co., Ltd. Internal BUS TB8 SBUF CL Zero Detector SHIFT START TX CONTROL ...
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UART : Mode 0 Timing [Transmit ...
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UART : Mode 1 Function Timer 1 Timer 2 Overflow Overflow 1 SMOD 0 1 TCLK T2CON RCLK T2CON.5 Semiconductor Co., Ltd. Internal BUS TB8 Write to SBUF SBUF CL Zero Detector ...
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UART : Mode 1 Timing [Transmit] TX Clock Write to SBUF S1 SEND Data Shift TXD Start bit TI [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift RI Semiconductor Co., Ltd ...
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UART : Mode 2 Function F OSC 1 SMOD (SMOD is PCON.7) Semiconductor Co., Ltd. Internal BUS TB8 Write to SBUF SBUF CL Zero Detector STOP BIT START TX CONTROL TX CLOCK 1/16 Serial ...
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UART : Mode 2 Timing [Transmit] TX Clock Write to SBUF SEND S1 Data Shift TXD Start bit TI Stop bit Gen. [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift RI Semiconductor Co., Ltd. ...
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UART : Mode 3 Function Timer 1 Timer 2 Overflow Overflow 1 SMOD 0 1 TCLK T2CON RCLK T2CON.5 Semiconductor Co., Ltd. Internal BUS TB8 Write to SBUF SBUF CL Zero Detector ...
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UART : Mode 3 Timing [Transmit] TX Clock Write to SBUF SEND S1 Data Shift TXD Start bit TI Stop bit Gen. [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift RI Semiconductor Co., Ltd. ...
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PCA (Programmable Counter Arrays) Basic Feature Support Intel/Philips compatible functions. [ PCA0 ] 16 bits MODULE0 16 bits MODULE1 Time Base for PCA Module MODULE2 PCA Timer/Counter MODULE3 MODULE4 P0.7 / ECI0 MODULE5 Module Functions: 16-bit Capture 16-bit Timer ...
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PCA : Interrupt Sources of a PCA CnMOD.0 .7 ECF CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 PCA Timer/Counter MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 MODULE5 ECCFm CnCAPMm.0 Semiconductor Co., Ltd. C0CON ( ACh) : PCA0 Counter Control Register ...
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PCA : PCAn Counter Control Registers To use a PCA Counter as an 8-bit Auto-reset Counter Turn off the PCAn by clearing CR bit (CnCON.6) Load target values into CnL and CnH. Set PWMDYN bit (CnMOD.6) and set CF ...
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PCA : PCAn Module Control Registers C0CAPM0 (A2h) : Mode Control Register of PCA0 MODULE0 IPWM0 ECOM0 CAPP0 CAPN0 MAT0 TOG0 R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) IPWM0 : Inverted PWM output. If this bit is set, ...
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PCA : PCA Modes 1) Capture Mode CF CnEXm IPWMm ECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm X 2) Compare/Timer Mode RESET Write to CnCAPmH 1 0 Write to CnCAPmL Semiconductor Co., Ltd. CnCON CR CCF5 CCF4 CCF3 CCF2 ...
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PCA : PCA Modes 3) PCA High Speed Output Mode RESET Write to CnCAPmH 1 0 Write to CnCAPmL [ Update of CnCAPmH & CnCAPmL During the interrupt routine, a new 16-bit compare value can be written to the ...
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PCA : PCA Modes 4) PWM Mode (Fixed : PWMDYN = PCA Timer/Counter (F CnL 8-BITCOMPARATOR CnCAPmL CnCAPmH CnCAPMm IPWMm ECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm PWM Mode (Dynamic : ...
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PCA : Examples of Fixed PWM Output Duty Cycle (CnCAPmH) with IPWMm = 0 100% (00) 90% (25) 50% (128) 10% (230) 0.4% (255) Duty Cycle (CnCAPmH) with IPWMm = 1 (Inverted PWM Output) 100% (00) 90% (25) 50% ...
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PCA : Examples of Dynamic PWM Output Duty Cycle (CnCAPmH) with IPWMm = 0, PWMDYN = 1, CnH = 47(0x2F). 100% (00) 83% (08) 50% (24) 17% (40) 2% (47) Duty Cycle (CnCAPmH) with IPWMm = 1, PWMDYN = ...
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ADC (Analog-to-Digital Converter) 8-channel 10-bit ADC (SAR Type) Max. 400ksps(samples per sec ADC ADCSEL (EDh) : ADC Clock and MUX Selection Register ADIV2 ADIV1 ADIV0 - - ADCS2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) ADCHEN (ECh) : ...
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ADC : Conversion Timing AD_EN Set by S/W AD_REQ Set by S/W AD_END Valid Bit Setup Time 5F ADC ADCF AD_EN : AD Conversion Enable Signal. Set or Cleared by S/W. AD_REQ : AD Conversion Request Bit. Set by ...
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Interrupt : 16 Sources / 4-level Priority Interrupt Sources : Timer 0/1/2, UART0/1, PCA0/1, ADC, WDT, LVD, 6 External. 4-level Interrupt Priority [Interrupt Vector Address] Interrupt Priority Address HIGH Sources Level LVD 0033h Highest INT0 0003h 4 Levels TF0 ...
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Interrupt Functional Description LVD (Power Fail) PFI INT0 IE0 Timer/Counter 0 TF0 INT1 IE1 Timer/Counter 1 TF1 RI UART0 TI Timer/Counter 2 TF2 ADC ADCF INT2 IE2 INT3 IE3 INT4 IE4 INT5 IE5 WDT WDIF RI1 UART1 TI1 PCA0 ...
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Reset Circuit : 3 Reset Sources LVD(POR) Reset Power-on Reset when power is turned on. Power-fail Reset when the supply voltage is below the threshold voltage (V ). RST External RESET Pin RESET Pin must be held “H” for ...
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Clock Circuit System Clock Sources External Oscillator or Crystal Internal Ring Oscillator Disable of External Clock (Crystal or External Oscillator) If XTOFF is set. When MCU is in stop mode and WDT is not active. IE.7 EA EIE.4 EWDT ...
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Clock Circuit : SFR IE (A8h) : Interrupt Enable Register EA EADC ET2 ES ET1 EX1 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W( Global interrupt enable EIE (E8h) : Extended Interrupt Enable Register - - - ...
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Clock Circuit : Guideline for Configuration Crystal Oscillator MiDAS XTAL2 XTAL1 Semiconductor Co., Ltd. Oscillator Module MiDAS XTAL2 XTAL1 OSC Oscillator Module Internal Ring Oscillator MiDAS XTAL2 RING XTAL1 OSC RC Oscillator [74] MiDAS2.0 Family ...
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Power Management : 3 Modes Active Mode : The CPU and The Peripherals operate. Idle Mode : The CPU is gated off from the clock signal. Only the Peripherals operate. Wake-up by activating any interrupt. The CPU resumes. Wake-up ...
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ISP (In-System Programming) Code memory (62KBytes) can be programmed using EJTAG in target system. EEPROM (2KBytes) can be programmed using EJTAG in target system. EJTAG Port VDD, VSS, MDS_SCK, MDS_SDA, PSEN [ISP Pin Configuration In GenICE52/MiDAS2.0] V (+3.3V) DD ...
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ISP : Command Set Command Blank Check the blank status of the device currently connected. Erases the device’s memory. Performs an erase chip, the device’s memory, both code and data. Erase Chip • Code • User data • Information ...
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IAP (In-Application Programming) IAP function is provided for the applications which need to save operation data/status in nonvolatile memory (on- chip EEPROM update application code (on-chip FLASH) by itself. Code memory(62KB) can be programmed or erased during ...
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IAP : Function Set IAP call address FFF0h IAP return value Success : [ACC] 8Xh Program Fail : [ACC] FCh Address fail : [ACC] FDh Lock fail : [ACC] FEh Command fail : [ACC] FFh Before calling IAP function, ...
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IAP : Coding Flow Set IAP Parameters FLASH_AEN Flag Set Call IAP Routine (FFF0h) FLASH_AEN Flag Clear Check IAP Return Value Semiconductor Co., Ltd. [Example Code : Program FLASH] MOV B, #03h ;IAP function setting MOV A, #55h ;Programmed ...
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Strong Points MiDAS 2.0 can reduce EMI by removing the needless swing of ALE signal. You can enable/disable ALE signal by changing the value of ALEOFF bit (SFR PMR.2). User can reduce system cost by removing needless decoupling capacitors ...
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Recommended Power Slope The supply voltage slope must be in the range from 0.0V/us to 1.0V/500us. (3.3V/1.65ms) (That is, the supply voltage should be increasing monotonically until it reaches to the normal range.) 3 500 us ...
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Absolute Maximum Ratings Absolute Maximum Ratings Symbol Parameter V DC supply voltage input voltage input current IN T Storage temperature STG Recommended Operating Conditions Symbol Parameter V DC supply voltage DD T Industrial ...
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DC Characteristics (5V Tolerant I/ 3.3 ± 0.3V, VEXT = 5V ± 0.25V (In case of P0, P1, P2, P3, RESET, PSEN, ALE, EA, MDS_SCK, MDS_SDA) Symbol Parameter High level input voltage Note1 V IH ...
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DC Characteristics (Normal I/ 3.3 ± 0.3V - (In case of XTAL2, P4, P5, P6, P7, P8, P9) Symbol Parameter High level input voltage V IH LVCMOS interface Low ...
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AC Characteristics * unless otherwise specified. A Parameter Symbol Operating Frequency F OSC RESET Input Width t RST External Interrupt t External Interrupt INT Input Width RESET 0.8V External Interrupt ...
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ADC Characteristics DC Electrical Characteristics Characteristics Resolution Differential Linearity Error Integral Linearity Error Offset Voltage Error (top) Offset Voltage Error (bottom) Channel to Channel Mismatch Analog Input Voltage AC Electrical Characteristics Characteristics Conversion Rate Conversion Time Dynamic Supply Current ...
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Package Dimensions : PLCC 44 pins Seating Plane Semiconductor Co., Ltd. 44-PLCC ...
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Package Dimensions : MQFP 44 pins 11 12 Seating Plane e Semiconductor Co., Ltd. 44-MQFP Notes [44-MQFP] ...
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Package Dimensions : 64 SPDIP E 64 pins Semiconductor Co., Ltd. 64-PDIP Base Plane Seating Plane e 1 [64-SPDIP] Dimension in Inches Dimension in ...
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Package Dimensions : LQFP 64 pins 16 17 Seating Plane e Semiconductor Co., Ltd. 64-LQFP Notes Dimension not include interlead flash. 2. Controlling ...
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Package Dimensions : TQFP 64 pins 16 17 Seating Plane e Semiconductor Co., Ltd. 64-TQFP Notes Dimension not include interlead flash. 2. Controlling ...
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Package Dimensions : 100 1 TQFP 100 pins 25 26 Seating Plane e b Semiconductor Co., Ltd. 100-TQFP Symbol Notes: 1. Dimension not include interlead flash. 2. ...
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Product Numbering System General Core MCU Series Core Type bits bits bits ROM Type 0 = ROMless 1 = ...
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Supporting tools MDS (Microprocessor Development System) In-Circuit Debugger Easy-to-Use GUI Application System On-board Implemented Various Application Various Sample Test Program Semiconductor Co., Ltd. Code Generation Tools Assembler & Linker for DOS & Windows Optimized Cross-C Compiler User-Friendly User-Friendly Development ...
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Appendix A : Instruction Set (1/19) Note on Instruction Set and Addressing Modes Notation Register the currently selected Register Bank (RB0 ~ RB3). Rn The address of 8-bit internal data location. direct This could be an ...
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Appendix A : Instruction Set (2/19) ADD A, <src-byte> Add ADD A, Rn Operation : (A) (A) + (Rn) ADD A, @Ri Operation : (A) (A) + ((Ri)) ADD A, direct Operation : (A) (A) + (direct) ADD A, #data ...
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Appendix A : Instruction Set (3/19) SUBB A, <src-byte> Subtract with Borrow SUBB A, Rn Operation : (A) (A) - (C) - (Rn) SUBB A, @Ri Operation : (A) (A) - (C) - ((Ri)) SUBB A, direct Operation : (A) ...
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Appendix A : Instruction Set (4/19) DEC <byte> Decrement DEC A Operation : (A) ( DEC Rn Operation : (Rn) (Rn DEC @Ri Operation : ((Ri)) ((Ri DEC direct Operation : (direct) (direct) - ...
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Appendix A : Instruction Set (5/19 Decimal-adjust Accumulator for Addition )>9] ∨ [(AC)=1]] IF [[(A 3-0 THEN (A Operation : 3-0 )>9] ∨ [(C)=1]] IF [[(A 7-4 THEN (A 7-4 ANL <dest-byte>, <src-byte> Logical AND for byte variables ...
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Appendix A : Instruction Set (6/19) ANL C, <src-bit> Logical AND for bit variables ANL C, bit Operation : (C) (C) ^ (bit) ANL C, /bit Operation : (C) (C) ^ ~(bit) ORL <dest-byte>, <src-byte> Logical OR for byte variables ...
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Appendix A : Instruction Set (7/19) ORL C, <src-byte> Logical OR for byte variables ORL C, bit (C) ∨ (bit) Operation : (C) ORL C, /bit (C) ∨ ~(bit) Operation : (C) XRL <dest-byte>, <src-byte> Logical Exclusive-OR for byte variables ...
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Appendix A : Instruction Set (8/19) CLR A Clear Accumulator Operation : (A) 0 CLR <bit> Clear bit CLR C Operation : (C) 0 CLR bit Operation : (bit) 0 CPL A Complement Accumulator Operation : (A) ~(A) CPL <bit> ...
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Appendix A : Instruction Set (9/19 Rotate Accumulator Left ( Operation : n RLC A Rotate Accumulator Left through the Carry flag ( n+1 n ...
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Appendix A : Instruction Set (10/19) MOV <dest-byte>, <src-byte> Move byte variable MOV A, Rn Operation : (A) (Rn) MOV A, @Ri Operation : (A) ((Ri)) MOV A, direct Operation : (A) (direct) MOV A, #data Operation : (A) data ...
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Appendix A : Instruction Set (11/19) MOV direct, @Ri Operation : (direct) ((Ri)) MOV direct, direct Operation : (direct) (direct) MOV direct, #data Operation : (direct) data MOV @Ri, A Operation : ((Ri)) (A) MOV @Ri, direct Operation : ((Ri)) ...
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Appendix A : Instruction Set (12/19) MOV DPTR, #data16 Load Data Pointer with a 16-bit constant (DPTR) data Operation : (DPH,DPL) (data MOVC <base-reg> Move Code byte MOVC DPTR Operation : (A) ((A) + ...
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Appendix A : Instruction Set (13/19) XCH A, <src-byte> Exchange Accumulator with byte variable XCH A, Rn (A) ↔ (Rn) Operation : XCH A, @Ri (A) ↔ ((Ri)) Operation : XCH A, direct (A) ↔ (direct) Operation : XCHD A, ...
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Appendix A : Instruction Set (14/19) SETB <bit> Set bit SETB C Operation : (C) 1 SETB bit Operation : (bit rel Jump if Carry is set (PC) (PC Operation : If ( then ...
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Appendix A : Instruction Set (15/19) JBC bit, rel Jump if Bit is set and Clear bit (PC) (PC Operation : If (bit then (bit) 0, (PC) ACALL addr11 Absolute Subroutine Call (PC) (PC ...
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Appendix A : Instruction Set (16/19) RET Return from Subroutine (PC ) ((SP)) 15-8 (SP) (SP Operation : (PC ) ((SP)) 7-0 (SP) (SP RETI Return from Interrupt (PC ) ((SP)) 15-8 (SP) (SP ...
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Appendix A : Instruction Set (17/19) JMP @A + DPTR Jump Indirect Relative to the DPTR Operation : (PC) (A) + (DPTR) JZ rel Jump if Accumulator is Zero (PC) (PC Operation : If (A)=0, then (PC) JNZ ...
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Appendix A : Instruction Set (18/19) CJNE <dest-byte>, <src-byte>, rel Compare and Jump if Not Equal CJNE A, direct, rel (PC) (PC (A) ≠ (direct), Operation : then (PC) If (A) < (direct), then (C) Else CJNE ...
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Appendix A : Instruction Set (19/19) DJNZ <byte>, rel Decrement and Jump if Not Zero DJNZ Rn, rel (PC) (PC Operation : (Rn) (Rn (Rn)≠0, then (PC) DJNZ direct, rel (PC) (PC (direct) ...
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Appendix B : SFR Description [80h ~ 87h] [How to Read a SFR Descriptions] Yellow Color : Bit Addressable SFR Address White Color : Byte Addressable P0 (80h) : Port 0 Register P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 R/W(1) R/W(1) ...
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Appendix B : SFR Description [88h ~ 8Dh] TCON (88h) : Timer/Counter 0/1 Control Register TF1 TR1 TF0 TR0 IE1 IT1 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) TF1 : Timer 1 overflow flag. TR1 : Timer 1 run ...
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Appendix B : SFR Description [8Eh ~ 91h] CKCON (8Eh) : Clock Control Register WD1 WD0 T2M T1M T0M - R/W(1) R/W(1) R/W(0) R/W(0) R/W(0) WD1, WD0 : Watchdog timer mode select [0, clocks (interrupt ...
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Appendix B : SFR Description [92h ~ 99h] C0CAP0L (92h) : Low Capture/Compare Register of PCA0 MODULE0 C0CAP0L.7 C0CAP0L.6 C0CAP0L.5 C0CAP0L.4 C0CAP0L.3 C0CAP0L.2 C0CAP0L.1 C0CAP0L.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) C0CAP1L (93h) : Low Capture/Compare Register of PCA0 MODULE1 C0CAP1L.7 ...
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Appendix B : SFR Description [9Ah ~ A1h] C0CAP0H (9Ah) : High Capture/Compare Register of PCA0 MODULE0 C0CAP0H.7 C0CAP0H.6 C0CAP0H.5 C0CAP0H.4 C0CAP0H.3 C0CAP0H.2 C0CAP0H.1 C0CAP0H.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) C0CAP1H (9Bh) : High Capture/Compare Register of PCA0 MODULE1 C0CAP1H.7 ...
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Appendix B : SFR Description [A2h ~ A7h] C0CAPM0 (A2h) : Mode Control Register of PCA0 MODULE0 IPWM0 ECOM0 CAPP0 CAPN0 MAT0 R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) IPWM0 : Inverted PWM output. If this bit is set, the PWM ...
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Appendix B : SFR Description [A8h ~ ADh] IE (A8h) : Interrupt Enable Register EA EADC ET2 ES ET1 EX1 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W( Global interrupt enable. EADC : ADC interrupt enable. ET2 : ...
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Appendix B : SFR Description [AEh ~ B4h] C0L (AEh) : Low Byte Register of PCA0 Counter C0L.7 C0L.6 C0L.5 C0L.4 C0L.3 C0L.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) C0H (AFh) : High Byte Register of PCA0 Counter ...
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Appendix B : SFR Description [B5h ~ BBh] P8 (B5h) : Port 8 Register P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) Bidirectional port with direction and pull-up control. P9 (B6h) : Port 9 ...
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Appendix B : SFR Description [BCh ~ C4h] P7DIR (BCh) : Port 7 Input/Output Control Register P7DIR.7 P7DIR.6 P7DIR.5 P7DIR.4 P7DIR.3 P7DIR.2 P7DIR.1 P7DIR.0 R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W( Input (Default Output ...
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Appendix B : SFR Description [C5h ~ CBh] STATUS (C5h) : Crystal Status Register - - - XTUP - - R(1) XTUP : Crystal oscillator warm-up status. It represents if the crystal clock is stable(1) or not(0). Cleared by H/W ...
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Appendix B : SFR Description [CCh ~ D0h] TL2 (CCh) : Timer/Counter 2 Low Byte Register TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) TH2 (CDh) : Timer/Counter 2 High Byte Register TH2.7 TH2.6 ...
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Appendix B : SFR Description [D2h ~ D9h] C1CAP0L (D2h) : Low Capture/Compare Register of PCA1 MODULE0 C1CAP0L.7 C1CAP0L.6 C1CAP0L.5 C1CAP0L.4 C1CAP0L.3 C1CAP0L.2 C1CAP0L.1 C1CAP0L.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) C1CAP1L (D3h) : Low Capture/Compare Register of PCA1 MODULE1 C1CAP1L.7 ...
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Appendix B : SFR Description [DAh ~ E1h] C1CAP0H (DAh) : High Capture/Compare Register of PCA1 MODULE0 C1CAP0H.7 C1CAP0H.6 C1CAP0H.5 C1CAP0H.4 C1CAP0H.3 C1CAP0H.2 C1CAP0H.1 C1CAP0H.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) C1CAP1H (DBh) : High Capture/Compare Register of PCA1 MODULE1 C1CAP1H.7 ...
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Appendix B : SFR Description [E2h ~ E7h] C1CAPM0 (E2h) : Mode Control Register of PCA1 MODULE0 IPWM0 ECOM0 CAPP0 CAPN0 MAT0 R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) IPWM0 : Inverted PWM output. If this bit is set, the PWM ...
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Appendix B : SFR Description [E8h ~ EEh] EIE (E8h) : Extended Interrupt Enable Register EPCA1 EPCA0 ES1 EWDT EX5 EX4 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) EPCA1 : PCA1 interrupt enable EPCA0 : PCA0 interrupt enable ES1 ...
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Appendix B : SFR Description [EFh ~ F8h] ADCON (EFh) : ADC Control & ADC Result Low Register : Value[1:0] AD_EN AD_REQ AD_END ADCF - - R/W(0) R/W(0) R(1) R/W(0) AD_EN : ADC enable. If reset, ADC is in stand-by ...
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Appendix C : Update History V1.2 Page 11~15, 65, 71~73 • PWM Contents Update Page 7, 11, 12, 16, 17, 96 • 44-TQFP 44-MQFP (Package Replacement) Page 7, 13, 18, 97 • 64-SPDIP 64-PDIP (Package Name ...