tspc603r ATMEL Corporation, tspc603r Datasheet - Page 10

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

9.2
Table 9-1.
Note:
9.3
10
PM Mode
Full Power
Full Power (with DPM)
Doze
Nap
Sleep
Programmable Power Modes
1. Exceptions are referred to as interrupts in the architecture specification.
Power Management Modes
TSPC603R
Power PC 603R Microprocessor Programmable Power Modes
Functioning Units
All units active
Requested logic by demand
- Bus snooping
- Data cache as needed
- Decrementer timer
Decrementer timer
None
The 603R provides four programmable power states, full power, doze, nap and sleep. The soft-
ware selects these modes by setting one (and only one) of the three power saving mode bits.
The hardware can enable a power management state through external asynchronous interrupts.
The hardware interrupt causes the transfer of program flow to interrupt the handler code. The
appropriate mode is then set by the software. The 603R provides a separate interrupt and inter-
rupt vector for power management, the System Management Interrupt (SMI). The 603R also
contains a decrement timer which allows it to enter the nap or doze mode for a predetermined
amount of time and then return to full power operation through the Decrementer Interrupt (DI).
Note that the 603R cannot switch from power-on management mode to another without first
returning to full on mode. The nap and sleep modes disable bus snooping; therefore, a hardware
handshake is provided to ensure coherency before the 603R enters these power management
modes.
Table 9-1
The following describes the characteristics of the 603R’s power management modes, the
requirements for entering and exiting the various modes, and the system capabilities provided
by the 603R while the power management modes are active.
Full Power Mode with DPM Disabled
Full power mode with DPM disabled; power mode is selected when the DPM enable bit (bit 11)
in HID0 is cleared
Full Power Mode with DPM Enabled
Full power mode with DPM enabled (HID0[11] = 1); provides on-chip power management with-
out affecting the functionality or performance of the 603R
• Default state following power-up and HRESET
• All functional units are operating at full processor speed at all times
• Required functional units are operating at full processor speed
summarizes the four power states.
–
Activation Method
By instruction dispatch
Controlled by SW
Controlled by hardware and
software
Controlled by hardware and
software
Full-power Wake-up Method
–
–
External asynchronous exceptions
Decrementer interrupt
Reset
External asynchronous exceptions
Decrementer interrupt
Reset
External asynchronous exceptions
Reset
5410B–HIREL–09/05
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