tspc603r ATMEL Corporation, tspc603r Datasheet - Page 36

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

Figure 12-2. Data Cache Organization
36
Block 0
Block 1
Block 2
Block 3
TSPC603R
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
128 sets
The instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes, an
address tag, and a valid bit. The instruction cache may not be written to except through a line fill
operation. The instruction cache is not snooped, and cache coherency must be maintained by
software. A fast hardware invalidation capability is provided to support cache maintenance. The
organization of the instruction cache is very similar to the data cache shown in
page
Each cache line contains eight contiguous words from memory that are loaded from an 8-word
boundary (that is, bits A27-A32 of the effective addresses are zero); thus, a cache line never
crosses a page boundary. Misaligned accesses across a page boundary can incur a perfor-
mance penalty.
The 603’s cache lines are loaded in four beats of 64 bits each. The burst load is performed as
“critical double word first”. The cache that is being loaded is blocked to internal accesses until
the load is completed. The critical double word is simultaneously written to the cache and for-
warded to the requesting unit, thus minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching device) implemen-
tation, the 603R implemements the MEI protocol. These three states, modified, exclusive, and
invalid, indicate the state of the cache block as follows:
Cache coherency is enforced by on-chip bus snooping logic. Since the 603R’s data cache tags
are single ported, a simultaneous load or store and snoop access represent a resource conten-
tion. The snoop access is granted first access to the tags. The load or store then occurs on the
clock following snoop.
• Modified - the cache line is modified with respect to system memory; that is, data for this
• Exclusive - this cache line holds valid data that is identical to the data at this address in-
• Invalid - this cache line does not hold valid data
address is valid only in the cache and not in the system memory
system memory. No other cache has this data
36.
State
State
State
State
8 words/block
Words 0-07
Words 0-07
Words 0-07
Words 0-07
Figure 12-2 on
5410B–HIREL–09/05