mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 16

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mpc2605

Manufacturer Part Number
mpc2605
Description
Integrated Secondary Cache Powerpc Microprocessors
Manufacturer
Micro Electronics Corporation
Datasheet

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DH0 – DH31,
MULTIPLE READ/WRITE HITS (NORMAL BUS MODE)
with multiple read hits. The MPC2605 supports only one
level of address pipelining for data transfer. Therefore, it
must hold off on its assertion of AACK for a pipelined TS until
MPC2605
16
DL0 – DL31
CPU DBG
L2 CLAIM
Figure 2 is an illustration of MPC2605 pipeline depth limit
CPU BG
A0 – A31
AACK
TBST
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
1
Figure 2. Multiple Burst Read (or Write) Hits
A
A1
2
A2
3
A3
4
B
the data tenure for the first TS is done. The MPC2605
asserts AACK at the same time as the fourth TA for data
tenures that it controls.
A4
5
6
B1
7
B2
8
C
B3
9
MOTOROLA
10
B4
11

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