mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 9

• Manufacturer Part Number: mpc2605
• Description: Integrated Secondary Cache Powerpc Microprocessors
• Manufacturer: Micro Electronics Corporation

NOTES:
NOTE: In all snoop push cases, BR is sampled the cycle after the ARTRY window. If BR is asserted in this cycle, L2 BR will be immediately negated
MOTOROLA
MPC2605 RESPONSE TO 60X TRANSFER ATTRIBUTES
MPC2605 RESPONSE TO CHIPSET TRANSFER ATTRIBUTES
TRANSFER ATTRIBUTES GENERATED FOR L2 COPYBACK
TT0 – TT4
X1X10
X1X10
X1010
X1010
00X10
X0010
X0010
00110
00110
00110
00010
00100
00100
00000
00000
01100
1. If a line fill is going to replace a dirty line and the cast out buffer (COB) is full, the line fill will be cancelled. (Unless the line fill is a write which
2. If a burst read misses the cache but hits the COB, the MPC2605 will supply the data from the COB, but not perform a line fill.
3. If ARTRY is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the to–be–replaced line will recover its old tag (valid,
4. If ARTRY is asserted during a read hit, the MPC2605 will abort the process.
5. If a processor burst write occurs right after a snoop write that was a cache hit, the MPC2605 will invalidate the line. If the snoop was a cache
6. If a processor burst write occurs right after a snoop read that was a cache hit, the MPC2605 will update the cache and clear the dirty bit.
TT0 – TT4
TT0 – TT4
hits in the COB. In this case, the line fill will occur.)
dirty, tag field), and the COB goes back to an invalid condition, even if the line fill is a burst write to the line in the COB.
miss, the MPC2605 will not perform a write allocate.
If the snoop was a cache miss, the MPC2605 will perform a write allocate.
X0010
X0010
X1010
X1010
0110X
00100
X1110
00100
X1110
00000
00000
00110
00010
and an assertion of L2 BG will be ignored.
TBST
X
X
X
X
X
X
0
0
1
1
0
0
0
1
1
1
Tag Status
Hit Clean
Hit Clean
Hit Dirty
Hit Dirty
TBST
CI
X
X
X
X
X
1
1
0
0
1
1
1
1
1
0
0
Hit
0
WT
X
X
X
X
X
1
0
0
0
X
X
X
X
X
X
X
Invalidate line
ARTRY and L2 BR write back data, invalidate line (see Note)
No action
ARTRY and L2 BR, write back data, reset dirty bit (see Note)
Invalidate (kill block)
Tag Status
Hit Clean
Hit Clean
Hit Clean
Hit Clean
Hit Clean
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
CI
1
Miss
Miss
Hit
Hit
Hit
Line–fill (processor read miss)
L2 CLAIM, AACK, TA (processor read hit)
Paradox — Invalidate the line (processor n–cacheable read hit
clean line)
Paradox — ARTRY, L2 BR, then write back data, invalidate the line
(processor n–cacheable read hit dirty line)
Line–fill except right after a snoop hit to processor (processor write
miss)
L2 CLAIM, AACK, TA except after a snoop hit to processor
(processor write hit)
Cache update (processor write through WT hit clean)
Cache update, clear dirty bit
Paradox — ARTRY, L2 BR, write back data, keep valid, clear dirty
bit
Paradox — Invalidate the line (processor n–cacheable write hit
clean line)
Paradox — ARTRY, L2 BR, then write back data, invalidate the line
(processor n–cacheable SB write hit dirty line)
Invalidate tag (flush block address–only)
ARTRY, L2 BR, write back data, invalidate tag (flush block
address–only)
No action (clean block address–only)
ARTRY, L2 BR, write back data, reset dirty bit (clean block
address–only)
Invalidate tag (kill block address–only)
WT
1
MPC2605 Response
MPC2605 Response
MPC2605
1, 3, 5, 6
Notes
1, 2, 3
5, 6
4
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