mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 25

• Manufacturer Part Number: mpc2605
• Description: Integrated Secondary Cache Powerpc Microprocessors
• Manufacturer: Micro Electronics Corporation

INSTRUCTION SET
cluded on this device. When the TAP (Test Access Port) con-
troller is in the SHIFT–IR state, the instruction register is
placed between TDI and TDO. In this state, the desired
instruction would be serially loaded through the TDI input.
TRST resets the TAP controller to the test–logic reset state.
The TAP instruction set for this device are as follows.
* Default state at power–up.
SAMPLE/PRELOAD TAP INSTRUCTION
scanning of the boundary–scan register without causing in-
terference to the normal operation of the chip logic. The
169–bit boundary–scan register contains bits for all device
signal and clock pins and associated control signals. This
register is accessible when the SAMPLE/PRELOAD TAP
instruction is loaded into the TAP instruction register in the
SHIFT–IR state. When the TAP controller is then moved to
the SHIFT–DR state, the boundary–scan register is placed
between TDI and TDO. This scan register can then be used
prior to the EXTEST instruction to preload the output pins
with desired values so that these pins will drive the desired
state when the EXTEST instruction is loaded. As data is writ-
ten into TDI, data also streams out TDO which can be used
to pre–sample the inputs and outputs.
CLAMP instruction to preload the values on the output pins
that will be driven out when the CLAMP instruction is loaded.
EXTEST TAP INSTRUCTION
junction with the SAMPLE/PRELOAD instruction to assist in
testing board level connectivity. Normally, the SAMPLE/
PRELOAD instruction would be used to preload all output
MOTOROLA
STANDARD INSTRUCTIONS
SAMPLE/PRELOAD
A five pin IEEE Standard 1149.1 Test Port (JTAG) is in-
The SAMPLE/PRELOAD TAP instruction is used to allow
SAMPLE/PRELOAD would also be used prior to the
The EXTEST instruction is intended to be used in con-
Instruction
BYPASS
EXTEST
CLAMP
HIGHZ
(Binary)
Code
1111*
0010
0000
1001
1100
Bypass instruction
Sample and/or preload
instruction
Extest instruction
High–Z all output pins while
bypass register is between
TDI and TDO
Clamp output pins while
bypass register is between
TDI and TDO
Description
TEST ACCESS PORT DESCRIPTION
pins. The EXTEST instruction would then be loaded. During
EXTEST, the boundary–scan register is placed between TDI
and TDO in the SHIFT–DR state of the TAP controller. Once
the EXTEST instruction is loaded, the TAP controller would
then be moved to the run–test/idle state. In this state, one
cycle of TCK would cause the preloaded data on the output
pins to be driven while the values on the input pins would be
sampled. Note the TCK, not the clock pin (CLK), is used as
the clock input while CLK is only sampled during EXTEST.
After one clock cycle of TCK, the TAP controller would then
be moved to the SHIFT–DR state where the sampled values
would be shifted out of TDO (and new values would be
shifted in TDI). These values would normally be compared to
expected values to test for board connectivity.
CLAMP TAP INSTRUCTION
signals driven from the output pins to be determined from the
boundary–scan register while the bypass register is selected
as the serial path between TDI and TDO. The signals driven
from the output pins will not change while the CLAMP
instruction is selected. EXTEST could also be used for this
purpose, but CLAMP shortens the board scan path by insert-
ing only the bypass register between TDI and TDO. To use
CLAMP, the SAMPLE/PRELOAD instruction would be used
first to scan in the values that will be driven on the output pins
when the CLAMP instruction is active.
HIGHZ TAP INSTRUCTION
to be placed in an inactive drive state (high–Z). During the
HIGH–Z instruction the bypass register is connected be-
tween TDI and TDO.
BYPASS TAP INSTRUCTION
power up. This instruction will place a single shift register
between TDI and TDO during the SHIFT–DR state of the
TAP controller. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
DISABLING THE TEST ACCESS PORT AND
BOUNDARY SCAN
pins used for the test access port. To circuit disable the
device, TCK must be tied to V SS to preclude mid level inputs.
TRST should be tied to V SS to ensure proper HRESET op-
eration. Although TDI and TMS are designed in such a way
that an undriven input will produce a response equivalent to
the application of a logic 1, it is still advisable to tie these
inputs to V DD through a 1K resistor. TDO should remain
unconnected.
The CLAMP instruction is provided to allow the state of the
The HIGH–Z instruction is provided to allow all the outputs
The BYPASS instruction is the default instruction loaded at
It is possible to use this device without utilizing the four
MPC2605
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