mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 23
mpc2605
Manufacturer Part Number
mpc2605
Description
Integrated Secondary Cache Powerpc Microprocessors
Manufacturer
Micro Electronics Corporation
Datasheet
1.MPC2605.pdf
(30 pages)
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READ HIT/WRITE HIT (WITHOUT CPU DBG PARKED)
is asserted in the same cycle that the processor asserts TS.
This implies CPU DBG is parked. In some systems it may not
be desirable or possible to park CPU DBG. Figure 9 shows
MOTOROLA
Most of the previous examples have assumed CPU DBG
DH0 – DH31,
DL0 – DL31
CPU DBG
L2 CLAIM
A0 – A31
CPU BG
AACK
TBST
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked
1
A
2
the response for a read hit from the MPC2605 is gated by the
assertion of CPU DBG. The fastest response possible in a
system that does not park CPU DBG is 3–1–1–1.
3
A1
4
A2
5
A3
6
A4
7
MPC2605
23