adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 53

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

DIGITAL AUDIO INTERFACE
The ADAU1373 provides three digital audio interface ports:
Digital Audio Interface A, Digital Audio Interface B, and Digital
Audio Interface C. Each port can receive and transmit audio data in
various serial formats. The ports can be configured as master or
slave, accommodating many possible system design combinations.
Each port has a frame clock (LRCLKA to LRCLKC), a bit clock
(BCLKA to BCLKC), and data receive and data transmit pins
(SDATAINA to SDATAINC and SDATAOUTA to SDATAOUTC)
available. The possible serial audio data formats are right justified,
left justified, I
set using Register 0x44 for Digital Audio Interface A, Register 0x45
for Digital Audio Interface B, and Register 0x46 for Digital Audio
Interface C. The serial data is received or transmitted MSB first,
followed by the remaining data bits. For more information about
the serial data input/output formats, see Figure 98 to Figure 100.
The registers allow each port to be set independently, as either
master or slave. In addition, these registers provide controls for
bit clock polarity, swapping left/right data, inverting the frame
clock, and adjusting data width. Figure 97 shows the audio
interface and ASRC block diagram.
f
BCLKA
DOUT_A
DIN_A
f
BCLK_B
DOUT_B
DIN_B
f
BCLK_C
DOUT_C
DIN_C
S_A_EXT
S_B_EXT
S_C_EXT
2
S, and DSP mode. The format for the ports can be
AIFCLKA
INTERFACE A
INTERFACE B
INTERFACE C
DIGITAL
DIGITAL
DIGITAL
AUDIO
AUDIO
AUDIO
AIFCLKB
(256 ×
f
S
)
f
BCLK_A
DOUT_A
DIN_A
f
BCLK_B
DOUT_B
DIN_B
f
BCLK_C
DOUT_C
DIN_C
S_A_INT
S_B_INT
S_C_INT
Figure 97. Digital Audio Interface and ASRC Block Diagram
ASRC CLK
(256 ×
ASRCA
ASRCB
ASRCC
f
S
)
Rev. 0 | Page 53 of 296
f
BCLK_DSP
DOUT_DSP
DIN_DSP
f
BCLK_DSP
DOUT_DSP
DIN_DSP
f
BCLK_DSP
DOUT_DSP
DIN_DSP
S_DSP
S_DSP
S_DSP
Digital Audio Interface A, Digital Audio Interface B, and Digital
Audio Interface C can go through the ASRC or directly to the
internal digital engine. The ASRCs on each port allow system
design flexibility to accommodate sample rates at the ports that
are different from those accommodated by the internal DSP.
The digital audio interface ports can be independently configured
as master or slave by using the MSx bit (Bit 6) in Register 0x44,
Register 0x45, and Register 0x46 for Digital Audio Interface A,
Digital Audio Interface B, and Digital Audio Interface C, respec-
tively. This allows a number of different options for using the
three ports.
When the ports are configured in master mode, the ports derive
the bit clock and frame clock using either AIFCLKA or AIFCLKB,
which are derived from PLLA and PLLB, respectively. The sample
rate can be selected using Bits[4:2] in Register 0x47, Register 0x48,
and Register 0x49 for Digital Audio Interface A, Digital Audio
Interface B, and Digital Audio Interface C, respectively.
In slave mode, the port accepts the bit clock and the frame clock
from the master in the system. If the ASRCs are enabled, the
port is not required to be synchronous to the master clock.
However, if the ASRCs are disabled, ensure that the port is
synchronous to the master in the system by providing the
master clock from the respective master.
AIFA_REC
AIFA_PB
AIFB_REC
AIFB_PB
AIFC_REC
AIFC_PB
MIX/MUX
DAC1
FDSP_CH2_DOUT
FDSP_CH2_DIN
FDSP_CH3_DOUT
FDSP_CH3_DIN
FDSP_CH4_DOUT
FDSP_CH4_DIN
DAC2
ENGINE
CODEC
DSP
DMCA
ADC/
FDSP CLK (128 × f
DMCB
ADAU1373
S
)