adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 58

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

ADAU1373
Post-HPFs
The post-HPF cutoff frequency is selectable via Register 0x7D,
Bits[7:3] as 3.7 Hz for dc removal or from 50 Hz up to 800 Hz,
with a 50 Hz step for low frequency component filtering. This
HPF block can be enabled or disabled for the left or right channel,
controlled by Register 0x7D, Bits[1:0]. The HPF calculates the
dc value of the signal, which is subtracted from the signal when
enabled. When the HPF block is disabled, Bit 2 of Register 0x7D
determines whether the calculated dc value is maintained and
subtracted from the input signal or cleared to 0.
Figure 105 shows the post-HPF frequency response plots for
various cutoff frequency settings.
DYNAMIC RANGE CONTROL (DRC)
The DRC is used to control the dynamic range of the signal.
It provides the capability to match the dynamic range of the
incoming signal with the dynamic range of the signal fed to the
next block or device without losing the signal-to-noise ratio.
The ADAU1373 provides three full-band DRCs or one multiband
DRC (MDRC). However, at any given time, either the three full-
band DRCs or the MDRC can be used. Register 0x80 through
Register 0xB2 are used for setting the MDRC or full-band DRCs.
The MDRC and the seven-band EQ share the same register
addresses (Register 0x80 through Register 0xBD). Therefore, for
the MDRC, ensure that the EQ coefficient writing enable bit
(EQ_WR_EN, Bit 0 in Register 0xBE) = 0; whereas for the
seven-band EQ, the EQ_WR_EN bit = 1.
–10
–15
–20
–25
–30
–35
–40
–5
0
20
Figure 105. Post-HPF Frequency Response
100
FREQUENCY (Hz)
50Hz TO 800Hz
(50Hz STEP)
HPF
1k
8kHz/20kHz
4kHz/
LPF
Figure 106. MDRC Block Diagram
5k
Rev. 0 | Page 58 of 296
FREQUENCY
|H(f)|
SPLITTER
MDRC
The MDRC provides a multiband dynamic range control by split-
ting the signal into three bands, depending on the frequency: low,
mid, and high. Each of the bands is processed separately, and
individual controls are provided for each band DRC. The MDRC
can be enabled or disabled by the MDRC_EN bit (Register 0xB2,
Bit 0) (see the MDRC block diagram in Figure 106).
The 3-band MDRC is composed of a second-order high-pass
IIR filter, a second-order low-pass IIR filter, the frequency
splitter, and three individual DRCs for low, mid, and high bands.
The 3 dB cutoff frequency of the HPF can be set from 50 Hz to
800 Hz in 50 Hz steps, configured using the MDRC_HPF bits
(Register 0xB0, Bits[5:2]).
The LPF cutoff frequency can be set to 4 kHz, 8 kHz, or 20 kHz
via the MDRC_LPF bits (Register 0xB0, Bits[1:0]).
The HPF and LFP can be enabled or disabled by using the
MDRC_LPFEN and MDRC_HPFEN bits in Register 0xB2.
The crossover frequencies between the low band and high band
are defined in Register 0xB1 by the MDRC_CROSS_LOW bits
(Bits[3:0]) and the MDRC_CROSS_HIGH bits (Bits[7:4]). The
crossover frequency between low band and mid band can be
varied from 100 Hz to 1600 Hz in steps of 100 Hz. The crossover
frequency for the mid-to-high bands can be varied from 1 kHz
to 16 kHz in steps of 1 kHz.
All of the previous frequency values are based on a 48 kHz
sampling rate. If the input signals are of a different sampling rate,
the values should be scaled accordingly.
Using the DRC
The ADAU1373 provides three DRCs that can be used as full band.
The DRCs are shared between full-band DRC or MDRC. When
the full-band DRCs are in use, the MDRC is not available. For full-
band DRC, the crossover filters can be disabled in Register 0xB2
via the MDRC_HPFEN bit (Bit 1) and the MDRC_LPFEN bit
(Bit 2). Each of the three DRCs has its own registers: Register 0x80
to Register 0x8F for DRC1, Register 0x90 to Register 0x9F for
DRC2, and Register 0xA0 to Register 0xAF for DRC3, plus enable
or disable bits, which are set by the DRCEN bits (Bits[1:0]) in
Register 0x8D, Register 0x9D, and Register 0xAD.
f
HIGH BAND
LOW BAND
MID BAND
DRC
DRC
DRC