tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 2

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

www.national.com
Connection Diagram
Pin Descriptions
V
V
GND
FS
FS
BCLK
MCLK
VF
VF
D
TS
D
CCLK
CI
CO
CC
BB
X
R
X
R
X
R
1
X
1
Pin
I
1
O
+5V
−5V
Ground. All analog and digital signals are referenced to this pin.
Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied
to this input to define the start of the transmit time slot assigned to this device (non-delayed data
timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot
assignment counter).
Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to
this input to define the start of the receive time slot assigned to this device (non-delayed data timing
mode), or the start of the receive frame (delayed data timing mode using the internal time-slot
assignment counter).
Bit clock input used to shift PCM data into and out of the D
kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK.
Master clock input used by the switched capacitor filters and the encoder and decoder sequencing
logic. Must be 512 kHz, 1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK.
The Transmit analog high-impedance input. Voice frequency signals present on this input are
encoded as an A-law or µ-law PCM bit stream and shifted out on the selected D
The Receive analog power amplifier output, capable of driving load impedances as low as 300Ω
(depending on the peak overload level required). PCM data received on the assigned D
decoded and appears at this output as voice frequency signals.
This transmit data TRI-STATE
assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted
out on the rising edges of BCLK.
Normally this open drain output is floating in a high impedance state except when a time-slot is active
on the D
This receive data input is inactive except during the assigned receive time slot of the assigned port
when the receive PCM data is shifted in on the falling edges of BCLK.
Control Clock input. This clock shifts serial control information into CI or out from CO when the CS
input is low, depending on the current instruction. CCLK may be asynchronous with the other system
clocks.
Control Data Input pin. Serial control information is shifted into COMBO II on this pin when CS is low.
Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data is
determined by bit 2 of byte 1, as defined in Table 1
Control Data Output pin. Serial control or status information is shifted out of COMBO II on this pin
when CS is low.
±
±
5% power supply.
5% power supply.
X
output, when the TS
See NS Package Number N20A
Order Number TP3076N-G
®
X
1 output pulls low to enable a backplane line-driver.
output remains in the high impedance state except during the
2
Description
00975804
R
and D
X
pins. BCLK may vary from 64
X
pin.
R
pin is