tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 3

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

Single Byte Power-Up/Down
Write Control Register
Read-Back Control Register
Write to Interface Latch Register
Read Interface Latch Register
Write Latch Direction Register
Read Latch Direction Register
Write Receive Gain Register
Read Receive Gain Register
Pin Descriptions
Functional Description
POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry initial-
izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed for no output, the power amp is
disabled and the device is in the non-delayed timing mode.
The Latch Direction Register (LDR) is pre-set with all IL pins
programmed as inputs, placing the SLIC interface pins in a
high impedance state. The CO pin is in TRI-STATE condi-
tion. Other initial states in the Control Register are indicated
in Section 2.0.
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in Table 1. It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D
TRI-STATE condition.
The data stored in the Gain Control registers, the LDR and
ILR, and all control bits remain unchanged in the power-
down state unless changed by writing new data via the serial
control port, which remains active. The outputs of the Inter-
face Latches also remain active, maintaining the ability to
monitor and control the SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
No external components are necessary to set the gain.
Following this is a programmable gain/attenuation amplifier
CS
IL3–IL0
Pin
Function
Chip Select input. When this pin is low, control information can be written to or read from COMBO II
via CI or CO.
Each Interface Latch I/O pin may be individually programmed as an input or an output determined by
the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever
control data is written to COMBO II, while CS is low, and the information is shifted out on the CO pin.
When configured as outputs, control data written into the ILR appears at the corresponding IL pins.
X
1 output is in the high impedance
(Continued)
X
I, is a high impedance input.
TABLE 1. Programmable Register Instructions
7
P
P
P
P
P
P
P
P
P
X
6
0
0
0
0
0
0
0
0
Byte 1 (Notes 1, 2, 3)
X
5
0
0
0
0
0
0
1
1
X
4
0
0
0
0
1
1
0
0
3
X
3
0
0
1
1
0
0
0
0
Description
which is controlled by the contents of the Transmit Gain
Register (see Programmable Functions section). An active
pre-filter then precedes the 3rd order high-pass and 5th
order low-pass switched capacitor filters. The A/D converter
has a compressing characteristic according to the standard
CCITT A or µ255 coding laws, which must be selected by a
control instruction during initialization (see Table 1 and Table
2). A precision on-chip voltage reference ensures accurate
and highly stable transmission levels. Any offset voltage
arising in the gain-set amplifier, the filters or the comparator
is canceled by an internal auto-zero circuit.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 µs (due to
the Transmit Filter) plus 125 µs (due to encoding delay),
which totals 290 µs. Data is shifted out on D
selected time slot on eight rising edges of BCLK.
DECODER AND RECEIVER FILTER
PCM data is shifted into the Decoder’s Receive PCM Reg-
ister via the D
falling edges of BCLK. The Decoder consists of an expand-
ing DAC with either A or µ255 law decoding characteristic,
which is selected by the same control instruction used to
select the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz sample and hold. A
programmable gain amplifier, which must be set by writing to
the Receive Gain Register, is included, and finally a Power
Amplifier capable of driving a 300Ω load to
load to
2
X
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
±
3.8V or a 15 kΩ load to
X
X
X
X
X
X
X
X
X
0
R
1 pin during the selected time-slot on the 8
7
6
5
Byte 2 (Note 1)
See Table 2
See Table 2
See Table 4
See Table 4
See Table 3
See Table 3
See Table 8
See Table 8
±
4.0V at peak overload.
4
None
3
±
X
3.5V, a 600Ω
1 during the
2
www.national.com
1
0