ucb1300 NXP Semiconductors, ucb1300 Datasheet - Page 24

• Manufacturer Part Number: ucb1300
• Description: Advanced Modem/audio Analog Front-end
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The ADC sync mode is particularly useful when the internal ADC has to be synchronized to the external system. Typically
it is used to synchronize the read-out of the touch screen to the driving of the LCD screen, which is normally placed
beneath the touch screen. Many spikes and a lot of 'noise' are superimposed on the touch screen signals, due to the
close coupling of the touch screen and the LCD.
The result of the conversion is stored in register 11 of the SIB interface, after the completion of the conversion. An
interrupt may be generated whenever a conversion is completed (ADC_FLA_INT and/or ADC_RIS_INT bits in
register 2 and 3) to ease the synchronization between the UCB1300 and the system controller. The ADC result is reset
to 0x000, whenever the ADC is started or armed till the ADC conversion is completed. ADC_DAT_VAL in the SIB
register 11 indicates the status of the ADC; it equals '0' when an ADC sequence is started, which implies that the ADC
result is not valid and it equals '1' when the ADC conversion is completed and the result is stored in the SIB register 11.
2000 Jun 26
adc_input_selection
Advanced modem/audio analog front-end
adc_start (internal)
adc_ena (internal)
‘adc start state’
adc_dat_valid
‘SIB frame’
‘adc state’
adc_sync
adc_data
Fig.18 ADC timing sequence, ADC sync mode, changing ADC input multiplexer settings.
tsibwrite
set adc_ena:1
thadcsync
wait for start
tadcena
tracking
tsibwrite
set adc_start:1
ttrckmin
24
wait for sync
tsibwrite
set adc_start:0
tadcsam3
tadcconv
conversion
wait for start
read reg:11
tracking
Product specification
UCB1300