isp1181 NXP Semiconductors, isp1181 Datasheet - Page 26

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 14:
[1]
[2]
[3]
[4]
[5]
[6]
[7]
9397 750 08938
Product data
Name
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read Scratch Register
Read Frame Number
Read Chip ID
Read Interrupt Register
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
In 8-bit bus mode this command requires more time to complete than other commands. See
During isochronous transfer in 16-bit mode, because N
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181.
Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
Command and register summary
12.1.1 Write/Read Endpoint Configuration
12.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1181 and to
perform a device reset.
This command is used to access the Endpoint Configuration Register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Destination
Error Code Register
endpoint 1 to 14
all registers with write access
Scratch Register
Frame Number Register
Chip ID Register
Interrupt Register
…continued
Rev. 04 — 30 October 2001
1023, the firmware must take care of the upper byte.
Table
15. A bus reset will disable all endpoints.
Code (Hex)
A2 to AF
B0
B2/B3
B4
B5
C0
Table
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
59.
Full-speed USB interface
Transaction
read 1 byte
write 2 bytes
write/read 2 bytes
read 1 or 2 bytes
read 2 bytes
read 4 bytes
Table
4). Automatic FIFO
ISP1181
[2]
[1]
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