isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 14

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Modes of operation
ISP1504A1_ISP1504C1_1
Product data sheet
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1504x1 ULPI bus can be programmed to operate in five modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1504x1 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
Table 4.
Signal
name
CLOCK
DATA[7:0]
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
ULPI signal description
Direction on
ISP1504x1
O
I/O
Rev. 01 — 6 August 2007
Signal description
60 MHz interface clock: During low-power and serial modes, the
clock can be turned off to save power.
8-bit data bus: In synchronous mode, the link drives DATA[7:0] to
LOW by default. The link initiates transfers by sending a nonzero data
pattern called TXCMD (transmit command). In synchronous mode, the
direction of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines
must be ignored for exactly one clock cycle whenever DIR changes
value. This is called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
Table
Section
4.
ISP1504A1; ISP1504C1
14. A description of the ULPI pin behavior in
ULPI HS USB OTG transceiver
Section
© NXP B.V. 2007. All rights reserved.
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