isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 17

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 7.
ISP1504A1_ISP1504C1_1
Product data sheet
Signal
TX_ENABLE
DAT
SE0
INT
Reserved
Signal mapping for 3-pin serial mode
8.1.5 Power-down mode
Maps to
DATA0
DATA1
DATA2
DATA3
DATA[7:4]
In this mode, the PHY will 3-state the DATA[7:0], CLOCK, NXT and DIR pins. The link can
reuse the 3-stated pins for other purposes. To enter power-down mode, the link must drive
the CS_N/PWRDN pin to HIGH. To exit power-down mode, the link must drive the
CS_N/PWRDN pin to LOW.
In this mode, the ISP1504x1 will do the following:
•
•
•
•
All internal circuits, including the internal regulator, are powered down. The total
current from V
The DATA[7:0], NXT, CLOCK and DIR pins are 3-stated and ignored. The STP pin is
ignored.
The pull-down resistors on DATA[7:0] are disabled.
USB wake-up events cannot be detected. The link must first wake up the ISP1504x1
by driving CS_N/PWRDN to LOW.
Direction
I
I/O
I/O
O
O
CC
is less than 10 A.
Rev. 01 — 6 August 2007
Description
active HIGH transmit enable
transmit differential data on DP and DM when TX_ENABLE is HIGH
receive differential data from DP and DM when TX_ENABLE is LOW
transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
receive single-ended zero from DP and DM when TX_ENABLE is LOW
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
reserved; the ISP1504x1 will drive these pins to LOW
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
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