isp1504c NXP Semiconductors, isp1504c Datasheet - Page 31

• Manufacturer Part Number: isp1504c
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1504A_ISP1504C_1
Product data sheet
Fig 12. Example of register write, register read, extended register write and extended register read
DATA[7:0]
CLOCK
NXT
AD indicates the address byte, and D indicates the data byte.
STP
DIR
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
register write
TXCMD
immediate
Figure 13
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register and setting
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0
on the bus (DP and DM connected to ground through 45 ). The host also sets
OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled
T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The Host Controller must interpret LINESTATE[1:0] as
shown in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
0
.
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
than 7 ms after reset time T
up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
extended
Table
13.
Rev. 01 — 19 October 2006
TXCMD
(REGR)
register read
immediate
0
. If the peripheral is in low-power mode, it must wake
D
ISP1504A; ISP1504C
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
Figure 13
© NXP B.V. 2006. All rights reserved.
004aaa710
does not
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