uja1079tw/5v0/wd NXP Semiconductors, uja1079tw/5v0/wd Datasheet
uja1079tw/5v0/wd
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uja1079tw/5v0/wd Summary of contents
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UJA1079 LIN core system basis chip Rev. 01 — 1 December 2009 1. General description The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a Local Interconnect Network (LIN) ...
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... NXP Semiconductors 2. Features 2.1 General Contains LIN ECU functions: LIN transceiver Scalable 3 voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB Watchdog with Window and Timeout modes and on-chip oscillator ...
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... Can operate at V ISO7637 pulse 4/4b and ISO16750-2 Stable output under all conditions 3. Ordering information Table 1. Ordering information Type number Package Name UJA1079TW/5V0/WD HTSSOP32 UJA1079TW/3V3/WD UJA1079TW/5V0 UJA1079TW/3V3 [1] UJA1079TW/5V0xx versions contain regulator (V1); UJA1079TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. UJA1079_1 Product data sheet voltages down to 4 ...
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... NXP Semiconductors 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF EN BAT DLIN LIN TXDL RXDL Fig 1. Block diagram UJA1079_1 Product data sheet EXT. PNP SYSTEM CONTROLLER BAT LIN Rev. 01 — 1 December 2009 UJA1079 LIN core system basis chip ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration 5.2 Pin description Table 2. Symbol i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN i.c. i.c. TEST1 WDOFF LIMP UJA1079_1 Product data sheet i. TXDL 4 V1 RXDL 5 RSTN 6 INTN UJA1079 9 SDI 10 SDO SCK 11 SCSN 12 i. i.c. 15 ...
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... NXP Semiconductors Table 2. Symbol WAKE1 WAKE2 i.c. i.c. i.c. GND i.c. LIN DLIN i.c. WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND ...
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... NXP Semiconductors The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in more detail in the following sections. UJA1079_1 Product data sheet Figure Rev. 01 — 1 December 2009 UJA1079 LIN core system basis chip 3. These modes are discussed in © ...
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... NXP Semiconductors V below BAT power-off threshold V th(det)poff (from all modes) high resistance V below BAT watchdog: OFF power-on threshold V th(det)pon LIN: Active/Lowpower successful watchdog: Window/ watchdog trigger Fig 3. UJA1079 system controller UJA1079_1 Product data sheet Overtemp V1: OFF limp home = LOW (active) LIN: Off and ...
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... NXP Semiconductors 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (V and the bus system high-resistive state. As soon as the battery supply rises above the power-on detection threshold (V the SBC goes to Standby mode, and a system reset is executed (reset pulse width long or short ...
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... NXP Semiconductors 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source is enabled (LIN or WAKE). Any attempt to enter Sleep mode while one of these conditions has not been satisfied will result in a short reset (3.6 ms min. pulse width ...
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... NXP Semiconductors SCS SCK 01 sampled SDI X MSB SDO X MSB floating Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. ...
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... NXP Semiconductors 6.2.3 WD_and_Status register Table 4. WD_and_Status register Bit Symbol Access Power-on default 15:13 A2, A1 000 WMC R/W 0 [1] 10:8 NWP R/W 100 7 SWR/WOS R V1S reserved WLS1 WLS2 R - 2:0 reserved R 000 [1] Bit NWP is set to it’s default value (100) after a reset. ...
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... NXP Semiconductors 6.2.4 Mode_Control register Table 5. Mode_Control register Bit Symbol Access Power-on default 15:13 A2, A1 001 12 RO R/W 0 11:10 MC R/W 00 [1] 9 LHWC R/W 1 [2] 8 LHC R ENC R LSC R WBC R PDC R/W 0 3:0 reserved R 0000 [1] Bit LHWC is set to 1 after a reset. [2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset. ...
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... NXP Semiconductors 6.2.5 Int_Control register Table 6. Int_Control register Bit Symbol Access Power-on default 15:13 A2, A1 010 V1UIE R reserved STBCL R reserved R 0 7:6 WIC1 R/W 00 5:4 WIC2 R reserved RTHC R WSE1 R/W 0 UJA1079_1 Product data sheet Description register address access status ...
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... NXP Semiconductors Table 6. Int_Control register Bit Symbol Access Power-on default 0 WSE2 R/W 0 6.2.6 Int_Status register [1] Table 7. Int_Status register Bit Symbol Access Power-on default 15:13 A2, A1 011 V1UI R reserved LWI R reserved R WI1 R POSI R WI2 ...
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... NXP Semiconductors 6.3 On-chip oscillator The on-chip oscillator provides the timing reference for the on-chip watchdog and the internal timers. The on-chip oscillator is supplied by an internal supply that is connected to V and is independent of V1. BAT 6.4 Watchdog (UJA1079/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms ...
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... NXP Semiconductors 6.4.2 Watchdog Timeout behavior The watchdog runs continuously in Timeout mode. It can be reset at any time by a watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set already pending, a system reset is performed. The watchdog is in Timeout mode when pin WDOFF is LOW and: • ...
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... NXP Semiconductors 6.5.1 RSTN pin A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a system reset is triggered internally. The reset pulse width (t generated undervoltage event (see (V > V BAT th(det)pon selected by connecting a 900 Ω ...
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... NXP Semiconductors 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4 The SBC can handle maximum voltages the voltage on pin BAT falls below the power-off detection threshold, V immediately enters Off mode, which means that the voltage regulator and the internal logic are shut down ...
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... NXP Semiconductors load current I PNP current Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0) Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor its current limit ...
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... The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor (β) of between 60 and 500 can be used ...
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... NXP Semiconductors The transmit data streams of the protocol controller at the TXDL input are converted by the transmitter into bus signals with optimized slew rate and wave shaping to minimize EME. 6.7.1.2 Lowpower/Off modes The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit STBCL = 1 (see Lowpower mode ...
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... NXP Semiconductors WBIAS pin WAKEx pin Wake-up int Fig 9. Wake-up pin sampling synchronized with WBIAS signal The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are sampled continuously). The sampling will be performed on the rising edge of WBIAS (see Figure 9) ...
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... NXP Semiconductors 6.9 Interrupt output Pin INTN is an active-LOW, open-drain interrupt output driven LOW when at least one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit in the Int_Status register interrupt status bit and not the pending wake-up. The pending wake-up is cleared on entering Normal mode and when the corresponding standby control bit (STBCL ...
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... NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions V voltage on pin x DC value x I reverse current from R(V1-BAT) pin V1 to pin BAT I current on pin DLIN DLIN V transient voltage on pins trt V electrostatic ...
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... NXP Semiconductors Table 8. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions T ambient amb temperature [1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-). [2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. ...
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... NXP Semiconductors 8. Thermal characteristics Layout conditions for R layer, board dimensions 129 × 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm × will reduce thermal resistance (see Fig 11 ...
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... NXP Semiconductors 90 R th(j-a) (K/ Fig 12. HTSSOP32 thermal resistance junction-to-ambient vs. PCB copper area UJA1079_1 Product data sheet without heatsink top layer with heatsink top layer Rev. 01 — 1 December 2009 UJA1079 LIN core system basis chip 015aaa138 PCB Cu heatsink area (cm ) © ...
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... NXP Semiconductors 9. Static characteristics Table 9. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Supply; pin BAT V battery supply voltage BAT I battery supply current BAT I additional battery supply ...
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... NXP Semiconductors Table 9. Static characteristics …continued − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter V power-on detection hysteresis hys(det)pon voltage V LIN undervoltage detection uvd(LIN) voltage V LIN undervoltage recovery uvr(LIN) ...
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... NXP Semiconductors Table 9. Static characteristics …continued − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Load regulation ΔV voltage variation on pin V1 V1 Line regulation ΔV voltage variation on pin V1 V1 PNP base ...
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... NXP Semiconductors Table 9. Static characteristics …continued − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Reset output with clamping detection; pin RSTN I HIGH-level output current OH I LOW-level output current ...
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... NXP Semiconductors Table 9. Static characteristics …continued − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter V input hysteresis voltage hys(i) R pull-up resistance pu LIN receive data output; pin RXDL I HIGH-level output current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 10. Dynamic characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Voltage source; pin V1 t undervoltage detection delay d(uvd) time t LOW-level clamping detection det(CL)L time Serial peripheral interface timing ...
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... NXP Semiconductors Table 10. Dynamic characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter δ2 duty cycle 2 δ3 duty cycle 3 δ4 duty cycle 4 t rising receiver propagation PD(RX)r delay t falling receiver propagation ...
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... NXP Semiconductors − PD(RX)sym PD(RX)r PD(RX)f [5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t period (or in the first half of the watchdog period). [6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Window mode only ...
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... NXP Semiconductors SCS t SPILEAD SCK SDI X floating SDO Fig 15. SPI timing 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. ...
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... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors temperature MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1079_1 Product data sheet maximum peak temperature = MSL limit, damage level ...
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... NXP Semiconductors 14. Revision history Table 13. Revision history Document ID Release date UJA1079_1 20091201 UJA1079_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 1 December 2009 UJA1079 LIN core system basis chip Supersedes - © NXP B.V. 2009. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.4 Control and Diagnostic features . . . . . . . . . . . . 2 2.5 Voltage regulator Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 System Controller . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.3 Standby mode 6.1.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 ...