uja1079tw/5v0/wd NXP Semiconductors, uja1079tw/5v0/wd Datasheet - Page 36

• Manufacturer Part Number: uja1079tw/5v0/wd
• Description: Lin Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[4]
[5]
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UJA1079_1
Product data sheet
Fig 14. Timing diagram LIN transceiver
output of receiving
output of receiving
t
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
PD(RX)sym
trig(wd)2
LIN bus signal
after the start of the watchdog period (watchdog overflows).
node A
node B
V
= t
V
TXDL
BAT
PD(RX)r
V
V
RXDL
RXDL
− t
PD(RX)f
Fig 13. Timing test circuit for LIN transceiver
.
t
t
PD(RX)f
bit
C
RXDL
Rev. 01 — 1 December 2009
t
PD(RX)r
t
bit
t
PD(RX)r
RXDL
TXDL
t
t
bus(rec)(min)
bus(rec)(max)
trig(wd)1
SBC
GND
BAT
t
, but not more than t
bit
DLIN
LIN
t
PD(RX)f
trig(wd)1
015aaa133
LIN core system basis chip
V
V
V
V
trig(wd)2
th(rec)RX(max)
th(dom)RX(max)
th(rec)RX(min)
th(dom)RX(min)
after the start of the watchdog
015aaa128
Table
, after the start of the
R
C
UJA1079
LIN
© NXP B.V. 2009. All rights reserved.
LIN
4); valid in watchdog
thresholds of
receiving node A
thresholds of
receiving node B
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