mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 62

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
10.5.4.3 DecoderControl register
10.5.4.4 BitPhase register
Controls decoder operation.
Table 84.
Table 85.
Selects the bit-phase between transmitter and receiver clock.
Table 86.
Table 87.
Bit
Symbol
Access
Bit
7
6
5
4 to 3 RxFraming[1:0]
2 to 1 00
0
Bit
Symbol
Access
Bit
7 to 0
Symbol
0
RxMultiple
ZeroAfterColl
RxCoding
Symbol
BitPhase
DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
DecoderControl register bit descriptions
BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation
BitPhase register bit descriptions
R/W
7
0
RxMultiple ZeroAfterColl
7
R/W
Rev. 3.4 — 26 January 2010
6
Value Description
-
0
1
1
01
-
0
1
defines the phase relationship between transmitter and receiver clock
Description
Remark: The correct value of this register is essential for proper
operation.
6
056634
this value must not be changed
after receiving one frame, the receiver is deactivated
enables reception of more than one frame
any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443 A
MIFARE or ISO/IEC 14443 A
this value must not be changed
Manchester encoding
BPSK encoding
R/W
5
5
RxFraming[1:0]
4
BitPhase[7:0]
4
R/W
R/W
3
3
2
ISO/IEC 14443 reader IC
2
R/W
00
MFRC531
© NXP B.V. 2010. All rights reserved.
1
1
RxCoding
R/W
62 of 116
0
0