mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 65

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
10.5.5.1 Page register
10.5.5.2 RxWait register
10.5.5.3 ChannelRedundancy register
10.5.5 Page 4: RF Timing and channel redundancy
Selects the page register; see
Selects the time interval after transmission, before the receiver starts.
Table 96.
Table 97.
Selects kind and mode of checking the data integrity on the RF channel.
Table 98.
Table 99.
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7 to 6 00
5
4
3
2
Symbol
CRC3309
CRC8
RxCRCEn
TxCRCEn
RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation
RxWait register bit descriptions
ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit
allocation
ChannelRedundancy bit descriptions
Symbol
RxWait[7:0]
R/W
7
7
00
R/W
Value
-
1
0
1
0
1
0
1
0
6
Rev. 3.4 — 26 January 2010
6
CRC3309
Function
this value must not be changed
CRC calculation is performed using ISO/IEC 3309
(ISO/IEC 14443 B)
CRC calculation is performed using ISO/IEC 14443 A
an 8-bit CRC is calculated
a 16-bit CRC is calculated
the last byte(s) of a received frame are interpreted as CRC bytes. If
the CRC is correct, the CRC bytes are not passed to the FIFO. If
the CRC bytes are incorrect, the CRCErr flag is set.
no CRC is expected
a CRC is calculated over the transmitted data and the CRC bytes
are appended to the data stream
no CRC is transmitted
R/W
056634
Section 10.5.1.1 “Page register” on page
5
Function
after data transmission, the activation of the receiver is delayed
for RxWait bit-clock cycles. During this frame guard time any
signal on pin RX is ignored.
5
CRC8
R/W
4
4
RxWait[7:0]
RxCRCEn TxCRCEn ParityOdd ParityEn
R/W
R/W
3
3
2
R/W
2
ISO/IEC 14443 reader IC
MFRC531
© NXP B.V. 2010. All rights reserved.
48.
R/W
1
1
65 of 116
R/W
0
0