max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 12

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

Table 5 describes the signals that provide data, status,
and control to the MAX2986 in RMII mode. In this
mode, data is transmitted and received in bit pairs. The
rMII mode connections are shown in Figure 9.
Integrated Powerline Digital Transceiver
Table 5. rMII Signal Description
Figure 9. MAC-PHY Connection in RMII Mode
12
MIIDAT[1:0]
MIITXEN
MIIDAT[5:4]
MIIRXDV
MIICLK
MANAGEMENT DATA UNIT
MIIMDC
MIIMDIO
NAME
______________________________________________________________________________________
LINES
DATA
2
1
2
1
1
1
1
Independent Interface (rMII)
I/O
I/O
O
O
I
I
I
I
802.3 MAC
ETHERNET
(RMII)
Transmit Data. Data are transferred to the interface from the external MAC across these two
lines, one di-bit at a time. MIIDAT[1:0] is 00 to indicate idle when MIITXEN is deasserted.
Transmit Enable. This signal indicates to the MAX2986 that valid data is present on the MIIDAT
pins. MIITXEN is asserted synchronously with the first nibble of the preamble and remains
asserted while all di-bits to be transmitted are presented to the rMII.
MII Receive Data. Data is transferred from the MAX2986 to the external MAC across these two
lines, one di-bit at a time. Upon assertion of MIIRXDV, the MAX2986 ensures that MIIDAT[5:4] =
00 until proper receive decoding takes place.
Receive Data Valid (CRS_DV). When asserted high, MIIRXDV indicates that the incoming data
on the MIIDAT pins are valid.
rMII Reference Clock. A continuous clock that provides the timing reference for MIIRXDV,
MIIDAT, MIITXEN, and MIIRXER. MIICLK is sourced by the Ethernet MAC or an external source
and its frequency is 5MHz (50MHz) in 10Mbps (100Mbps) data rate.
MII Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal.
MII Management Data Input/Output. It is a bidirectional signal that carries the data for the
management data interface.
Reduced Media
CLOCK SOURCE (5MHz OR 50MHz)
REFCLK
TXEN
CRS_DV
TXD[1:0]
RXD[1:0]
MDC
MDIO
MIIDAT[1:0]
MIIDAT[5:4]
V
MIIRXDV
MIIMDIO
CC
MIITXEN
MIIMDC
MIICLK
BUFWR
BUFRD
BUFCS
In case of an error in the received data, to eliminate the
requirement for MIIRXER and still meet the requirement
for undetected error rate, MIIDAT[5:4] replaces the
decoded data in the receive stream with 10 until the end
of carrier activity. By this replacement, the CRC check is
guaranteed to detect an error and reject the packet.
INTERFACE
rMII
DESCRIPTION
MAX2986
MAC
PHY