max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 14

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

When the external host is ready to transmit a frame and
MIICRS is low (the previous transmission is finished), it
asserts MIITXEN. The external host must assert MIITXEN
if MIIRXDV is not high to avoid data loss. In response,
MIICRS is asserted by the MAX2986. While the external
host keeps MIITXEN high, 1 byte of data is transmitted
into the MAX2986 through MIIDAT for each positive
Integrated Powerline Digital Transceiver
Figure 10. Buffering Transmission Process from the External
Host View
Figure 11. Transmission Timing of the Buffering (FIFO) Interface
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______________________________________________________________________________________
NO
1
AVAILABLE?
MIITXEN
ASSERT
CRS OR
START
FRAME
RXDV
FIFO Signal Timing—Transmitting
YES
0
MIITXEN
MIICRS
BUFWR
MIIDAT
NO
FRAME LENGTH
WRITE TO THE
DATA
INTERFACE
COUNTER =
MIITXEN
RESET
FIFO
YES
DATA
DATA
edge of
data, the external host resets MIITXEN. Interactions
between the external host and the MAX2986 baseband
chip are shown in Figure 10.
The overall transmission timing of the FIFO interface is
illustrated in Figure 11 with detailed timing shown in
Figure 12 and Table 7.
Figure 12. FIFO Interface—Detailed Transmit Timing
Table 7. FIFO Interface —Transmit Timing*
* Per IEEE 802.3u standard.
** The default value of the debounce parameter is 3.
PARAMETER
DATA
t
t
IH
IS
MIITXEN
BUFWR. After transmission of the last byte of
BUFWR
MIIDAT
DATA
Setup prior to positive
edge of BUFWR
Hold after positive
edge of BUFWR
DESCRIPTION
t
IS
t
IH
Debounce**
MIICLK
TYP
+ 3
3
UNITS
ns
ns