max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 13

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

rMII transmit and receive timing are the same as for MII,
except that the data are sent and received in 2-bit
format and MIICRS is removed.
Table 6 describes signals that provide data, status, and
control to and from the MAX2986 in buffering (FIFO)
mode. The FIFO buffering interface is operated in half-
duplex mode. MIIRXDV is never asserted at the same
time as MIITXEN, but it is able to start transmission
while receive is in progress. It is highly recommended
to give reception a higher priority to avoid data loss.
On transmit, the MAX2986 asserts MIICRS after MIITXEN
is asserted, and drops it after MIITXEN is deasserted
and when the MAX2986 is ready to get another packet.
When MIICRS falls, it can be asserted again if there is
another packet to send.
Table 6. FIFO Signal Description
MIIDAT[7:0]
MIITXEN
MIICRS
BUFWR
MIIRXDV
MIIRXER
BUFRD
BUFCS
MIICLK
NAME
LINES
DATA
8
1
1
1
1
1
1
1
1
Integrated Powerline Digital Transceiver
______________________________________________________________________________________
I/O
I/O
O
O
O
I
I
I
I
I
Transmit/Receive Data. Data are transferred to/from the MAX2986 from/to the external MAC
across this bidirectional port, one byte at a time.
Transmit Enable [Active High]. This signal indicates to the MAX2986 that the transmission has
started, and that data on MIIDAT should be sampled using BUFWR. MIITXEN remains high to
the end of the session.
Transmit In Progress [Active High]. When asserted high, MIICRS indicates to the external
host that outgoing traffic is present on the powerline and the host should wait until the signal
goes low before sending additional data.
Write [Active Low]. Inputs a write signal to the MAX2986 from the external MAC, writing the
present data on MIIDAT pins into the interface buffer on each positive edge.
Receive Data Valid [Active High]. When asserted high, MIIRXDV indicates that the incoming
data on the MIIDAT pins are valid.
Receive Error [Active High]. When asserted high, MIIRXER indicates to the external MAC that
an error has occurred during the frame reception.
Read [Active Low]. Inputs a read signal to the MAX2986 from the external MAC, reading the
data from the MIIDAT pins of the MAX2986 on each positive edge.
Chip Select [Active Low]. When asserted low, it enables the chip.
Reference Clock. Used for sampling BUFWR and BUFRD.
FIFO Interface Signals
rMII Signal Timing
Transmissions are modulated onto the wire as soon as
the transfer begins, as the interface fills the MAX2986
buffer faster than data needs to be made available to
the modulator. When a packet arrives at the MAX2986,
it attempts to gain access to the channel. Since this
may not happen before the entire packet is transferred
across the interface, the MAX2986 buffers at least one
Ethernet packet to perform this rate adaptation.
On receive; when the MAX2986 anticipates that it will
have a packet demodulated, it raises MIIRXDV to iden-
tify the upper layer that a packet is ready to transmit.
MIIRXDV drops when the last byte is transmitted.
Receive direction transfers have priority over the transmit
direction to ensure that the buffer empties faster than
packets arrive. The minimum receive time is one Tx frame
plus an IFG.
DESCRIPTION
13