max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 8

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

MIIRXDV are high), the external host must wait until the
completion of reception and the deassertion of MIICRS
before starting a transmission. When sending two con-
secutive frames, the minimum time the external host
needs to wait is the one-frame transfer time plus an
interframe gap.
Note: For information such as signal timing characteris-
tics and electrical characteristics, refer to the IEEE
802.3u.
Note: The MII signals MIICOL and MIITXER are not
used, as the powerline networking device is able to
detect and manage all transmission failures. The sig-
nals MIITXCLK and MIIRXCLK have the same source
and are referred to as MIICLK in this document.
In MII mode, the data is transferred synchronously with
a 2.5MHz/25MHz clock. Data transmission in MII is in
Integrated Powerline Digital Transceiver
Table 1. Upper Layer Interface-Selection Pin Settings
Table 2. MII Signal Description
8
MIIDAT
[3:0]
MIITXEN
MIICRS
MIIDAT
[7:4]
MIIRXDV
MIIRXER
MIICLK
MANAGEMENT DATA UNIT
MIIMDC
MIIMDIO
NAME
_______________________________________________________________________________________
INTERFACE
LINES
4
1
1
4
1
1
1
1
1
FIFO
rMII
MII
I/O
I/O
O
O
O
O
I
I
I
I
Transmit Data. Data are transferred to the MAX2986 from the external MAC across these four lines,
one nibble at a time, synchronous to MIICLK.
Transmit Enable. Provides the framing for the Ethernet packet from the Ethernet MAC. This signal
indicates to the MAX2986 that valid data is present on MIIDAT[3:0] and must be sampled using
MIICLK.
Carrier Sense. Logic-high indicates to the external host that traffic is present on the powerline and the
host must wait until the signal goes invalid before sending additional data. When a packet is being
transmitted, MIICRS is held high.
Receive Data. Data are transferred from the MAX2986 to the external MAC across these four lines, one
nibble at a time, synchronous to MIICLK. The MAX2986 properly formats the frame so the Ethernet
MAC is presented with the expected preamble plus the start frame delimiter (SFD).
Receive Data Valid. Logic-high indicates that the incoming data on the MIIDAT pins are valid.
Receive Error. Logic-high indicates to the external MAC that the MAX2986 detected a decoding error
in the receive stream.
Reference Clock. A 2.5MHz (25MHz) clock in 10Mbps (100Mbps) as reference clock.
Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal.
Management Data Input/Output. A bidirectional signal that carries the data for the management data
interface.
GPIO[3]
0
0
0
nibble format so the data transmission rate is
10Mbps/100Mbps.
In rMII mode, the data is transferred synchronously with
a 5MHz/50MHz clock. Data transmission in MII is in
2-bit format so the data transmission rate is
10Mbps/100Mbps.
In FIFO mode, data is read and written in byte format
on each positive edge of BUFRD and BUFWR. The only
limitation in this mode is that BUFRD and BUFWR must
be low for at least three pulses of MIICLK to be consid-
ered a valid signal.
The upper layer interface can be selected according to
the settings shown in Table 1.
Table 2 describes the signals that provide data, status,
and control to and from the MAX2986 in MII mode.
DESCRIPTION
GPIO[6]
0
1
1
MII Interface Signals
GPIO[4]
1
0
1