mc13109 Freescale Semiconductor, Inc, mc13109 Datasheet - Page 16

• Manufacturer Part Number: mc13109
• Description: Universal Cordless Telephone Subsystem
• Manufacturer: Freescale Semiconductor, Inc

PLL I/O Pin Specifications
normally powered by the internal voltage regulator at the
“PLL V ref ” pin. The “PLL V ref ” pin is the output of a voltage
regulator which is powered from the “V CC Audio” power
supply pin. Therefore, the maximum input and output levels
for most PLL I/O pins (LO 2 In, LO 2 Out, R x PD, T x PD, T x
VCO) is the regulated voltage at the “PLL V ref ” pin. The ESD
protection diodes on these pins are also connected to “PLL
V ref ”. Internal level shift buffers are provided for the pins
(Data, Clk, EN, Clk Out) which connect directly to the
microprocessor. The maximum input and output levels for
these pins is V CC . Figure 9 shows a simplified schematic of
the PLL I/O pins.
Microprocessor Serial Interface
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The “Data” and “Clk” pins are used to load
data into the shift register. Figure 10 shows “Data” and “Clk”
pin timing. Data is clocked on positive clock transitions.
R x PD, T x PD and
ELECTRICAL CHARACTERISTICS
PLL PIN INTERFACE
PLL LOOP
I/O
LO 2 In, LO 2 Out,
EN to Clk Setup Time
Data to Clk Setup Time
Hold Time
Recovery Time
Input Pulse Width
Input Rise and Fall Time
MPU Interface Power–Up
2nd LO Frequency
“T x VCO” Input Frequency
16
The 2nd LO, R x and T x PLL’s and MPU serial interface are
The “Data”, “Clk”, and “EN” pins provide an MPU serial
Delay
T x VCO Pins
Figure 9. PLL I/O Pin Simplified Schematics
PLL V ref
Characteristic
Characteristic
(2.2 V)
In
(2.0 to 5.5 V)
V CC Audio
Data, Clk, and EN Pins
2.0 A
90% of PLL V ref to
V in = 200 mV pp
PLL V ref
Data, Clk, EN
(2.2 V)
Condition
Condition
(continued) (V CC = 2.6 V, T A = 25 C)
–
–
–
–
–
–
–
(2.0 to 5.5 V)
V CC Audio
Clk Out Pin
1.0 k
MC13109
Data, Clk
Data, Clk
Measure
Measure
LO 2 Out
T x VCO
EN, Clk
EN, Clk
EN, Clk
LO 2 In
Out
Data
Clk
Pin
Pin
EN
–
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 11 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Clk, EN
After data is loaded into the shift register, the data is
Symbol
t puMPU
Symbol
f txmax
Data,
t suEC
t suDC
Clk
Data
EN
Figure 10. Data and Clock Timing Requirement
t rec
t r , t f
f LO
Clk
t suEC
t w
t h
Figure 11. Enable Timing Requirement
t suDC
50%
t r
50%
50%
MOTOROLA ANALOG IC DEVICE DATA
Clock
10%
Last
Min
Min
200
100
100
90
90
–
–
–
–
–
–
50%
90%
50%
50%
t rec
Previous Data Latched
Max
Max
100
9.0
12
80
–
–
–
–
–
–
–
t f
t h
Clock
First
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
s
s