mc13109 Freescale Semiconductor, Inc, mc13109 Datasheet - Page 24

• Manufacturer Part Number: mc13109
• Description: Universal Cordless Telephone Subsystem
• Manufacturer: Freescale Semiconductor, Inc

Test Modes
of internal counters and set AGC Gain Options. In test
mode, the “T x VCO” input pin is multiplexed to the input of
the counter under test and the output of the counter under
test is multiplexed to the “Clk Out” output pin so that each
counter can be individually tested. Make sure test mode bits
are set to “0” for normal operation. Test mode operation is
described in Figure 31. During normal operation and when
testing the T x Prescaler, the “T x VCO” input can be a
minimum of 200 mV pp at 80 MHz and should be ac coupled.
For other test modes, input signals should be standard logic
levels of 0 to 2.2 V and a maximum frequency of 16 MHz.
NOTE:
TM #
24
10
Test Mode Control latch bits enable independent testing
0
1
2
3
4
5
6
7
8
9
R
Register
Mode
Gain
Ref
TM
R x
T x
i
To determine the correct output, look at the lower 8 bits in the R x or T x register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
TM 3
0
0
0
0
0
0
0
0
1
1
1
TM 2
C
Count
0
0
0
0
1
1
1
1
0
0
0
9966
7215
2048
N/A
N/A
N/A
TM 1
0
0
1
1
0
0
1
1
0
0
1
15
–
–
–
–
–
–
TM 0
0
1
0
1
0
1
0
1
0
1
0
14
–
–
–
0
–
–
Normal Operation
R x Counter, upper 6
R x Counter, lower 8
R x Prescaler
T x Counter, upper 6
T x Counter, lower 8
T x Prescaler
Reference Counter
Divide by 4, 25
AGC Gain = 10 Option
AGC Gain = 25 Option
Figure 32. Latch Register Power–Up Defaults
13
Counter Under Test or
1
0
0
0
–
–
Test Mode Option
Figure 31. Test Mode Description
12
0
1
0
0
–
–
MSB
11
0
1
1
0
–
–
MC13109
10
1
1
0
1
–
–
9
1
0
0
1
–
–
Power–Up Defaults for Control and Counter Registers
initialized to a defined state. The MC13109 is initially placed in
the Rx mode with all mutes active and nothing disabled. The
reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output frequency.
The T x and R x latch registers are set for USA Channel
Frequency #21. Figure 32 shows the initial power–up states
for all latch registers.
When the IC is first powered up, all latch registers are
Input Signal
>200 mV pp
>200 mV pp
“T x V CO ”
0 to 2.2 V
0 to 2.2 V
0 to 2.2 V
0 to 2.2 V
0 to 2.2 V
0 to 2.2 V
0 to 2.2 V
8
0
0
0
0
–
–
N/A
N/A
7
1
0
0
1
–
–
MOTOROLA ANALOG IC DEVICE DATA
6
1
0
0
1
–
0
Input Frequency/64
See Note Below
Input Frequency/4
Input Frequency/64
See Note Below
Input Frequency/4
Input Frequency/Reference Counter Value
Input Frequency/100
5
1
1
0
1
–
0
“Clk Out” Output Expected
4
0
0
0
0
1
0
LSB
3
1
1
0
1
0
0
–
–
–
2
1
1
0
1
1
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0